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教程资料 FPGA设计重利用方法(Design Reuse Methodology)
 
FPGAs have changed dramatically since Xilinx first introduced them just 15 years ago. In thepast, FPGA were primarily used for prototyping and lower volume applications; custom ASICswere used for high volume, cost sensitive designs. FPGAs had also been too expensive and tooslow for many a ...
可编程逻辑 FPGA设计重利用方法(Design Reuse Methodology)
 
FPGAs have changed dramatically since Xilinx first introduced them just 15 years ago. In thepast, FPGA were primarily used for prototyping and lower volume applications; custom ASICswere used for high volume, cost sensitive designs. FPGAs had also been too expensive and tooslow for many a ...
VHDL/FPGA/Verilog Genode FX is a composition of hardware and software components that enable the creation of fully fl
Genode FX is a composition of hardware and software components that enable
the creation of fully fledged graphical user interfaces as system-on-chip
solutions using commodity FPGAs.
ALTERA FPGA开发软件 Libero IDE 8.60
Actel Corporation Libero 集成设计环境(IDE) 为 FPGA 设计。新版本提供 SmartDesign, 使用户设计在一个更高的水平抽象。新工具随员支持所有Actel 的FPGAs, 包括并且基于闪光的, 低功率ProASIC3 和5 微瓦特Actel 园屋顶的小屋FPGAs, 单片Actel 融合PSC (可编程序的系统芯片) ...
电源技术 低电压FPGA的高性能开关电源解决方案
 
The core voltages for FPGAs are moving lower as a resultof advances in the fabrication process. The newest FPGAfamily from Altera, the Stratix® II, now requires a corevoltage of 1.2V and the Stratix, Stratix GX, HardCopy®Stratix and CycloneTM families require a core voltage of1.5V ...
系统设计方案 1.an fpga implementation of the image space reconstruction algorithm for hyperspectral imaging analy
1.an fpga implementation of the image space reconstruction algorithm for hyperspectral imaging analysis
2. fpga implemention of a median filter
3. fpga implementation of digital filters
4.hardware acceleration of edge detection algorithm on fpgas
5.implementation and evaluation of image processing a ...
技术资料 Libero IDE 9.1
Actel Corporation Libero 集成设计环境(IDE) 为 FPGA 设计。新版本提供 SmartDesign, 使用户设计在一个更高的水平抽象。新工具随员支持所有Actel 的FPGAs, 包括并且基于闪光的, 低功率ProASIC3 和5 微瓦特Actel 园屋顶的小屋FPGAs, 单片Actel 融合PSC (可编程序的系统芯片) ...
精品软件 LIBERO IDE 8.60
Actel Corporation Libero 集成设计环境(IDE) 为 FPGA 设计。新版本提供 SmartDesign, 使用户设计在一个更高的水平抽象。新工具随员支持所有Actel 的FPGAs, 包括并且基于闪光的, 低功率ProASIC3 和5 微瓦特Actel 园屋顶的小屋FPGAs, 单片Actel 融合PSC (可编程序的系统芯片) ...
教程资料 在多FPGA阵列上实现SAR距离脉压
SAR-GMTI_Range_Compression_Implementation_in_FPGAs\\r\\n\\r\\n在多FPGA阵列上实现SAR距离脉压，超长点数脉压的FPGA实现
教程资料 The DSP Design Flow workshop provides
The DSP Design Flow workshop provides an introduction to the advanced tools you need to design and implement DSP algorithms targeting FPGAs. This intermediate workshop in implementing DSP functions focuses on learning how to use System Generator for DSP,