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VHDL/FPGA/Verilog 基于Verilog-HDL的硬件电路的实现 9.7 步进电机的控制 9.7.1 步进电机驱动的逻辑符号 9.7.2 步进电机驱动的时序图 9.7.3 步进电机驱动的逻辑框图
基于Verilog-HDL的硬件电路的实现
9.7 步进电机的控制
9.7.1 步进电机驱动的逻辑符号
9.7.2 步进电机驱动的时序图
9.7.3 步进电机驱动的逻辑框图
9.7.4 计数模块的设计与实现
9.7.5 译码模块的设计与实现
9.7.6 步进电机驱动的Verilog-HDL描述
9.7.7 编译指令-"宏替换`define"的使用 ...
编译器/解释器 Jode Decompiler.安装方法：点击Eclipse的Help菜单 --> Software Updates --> Find and install...
Jode Decompiler.安装方法：点击Eclipse的Help菜单 --> Software Updates --> Find and install...，然后选择：Search for new features to install，在弹出的对话框中点击"New Remote Site..."菜单。填入：Name: Jode DecomopilerURL: http://www.technoetic.com/eclipse/update点击"Finish"。之后可以在Window菜单的Prefe ...
嵌入式/单片机编程 First of all we would like to thank God Almighty for giving us the strength and confidence in pursi
First of all we would like to thank God Almighty for giving us the strength and confidence in
pursing the ambitions. We would like to thank our Examiner Professor Axel Jantsch for
allowing us to do this under his guidance and encouragement. At the same time we would like
to mention our sincere thank ...
Linux/Unix编程 看n2实例 #Create a simulator object set ns [new Simulator] #Define different colors for data flows
看n2实例 #Create a simulator object
set ns [new Simulator]
#Define different colors for data flows
#$ns color 1 Blue
#$ns color 2 Red
#Open the nam trace file
set nf [open out-1.nam w]
$ns namtrace-all $nf
set f0 [open out0.tr w]
set f1 [open out1.tr w]
#Define a finish procedure
proc finish {} ...
VHDL/FPGA/Verilog SOPC实验--Hello World实验:启动Quartus II软件
SOPC实验--Hello World实验:启动Quartus II软件，选择File→New Project Wizard，在出现的对话框中填写项目名称 2、 点击Finish，然后选择“是”。选择Assignments→Device，改写各项内容。Family改为CycloneII，根据实验板上的器件选择相应的器件，本实验选择EP2C5T144C8,点击对话框中的Device & Pin Options，在Configura ...
操作系统开发 在采用多道程序设计的系统中
在采用多道程序设计的系统中，往往有若干个进程同时处于就绪状态。当就绪进程个数大于处理机数时，就必须依照某种策略来决定哪些进程优先占用处理机。本实验模拟在单处理机情况下的处理机调度，帮助学生加深了解处理机调度的工作。
二、实验类型
设计型。
三、预习内容
预习课本处理机调度有关内容，包括进程占用处理机的 ...
软件设计/软件工程 Learn how to leverage a key Java technology used to access relational data from Java programs, in
Learn how to leverage a key Java technology used to access
relational data from Java programs, in an Oracle environment.
Author Donald Bales begins by teaching you the mysteries of
establishing database connections, and how to issue SQL queries
and get results back. You ll move on to advanced to ...
VC书籍 Using Trolltech s Qt you can build industrial-strength C++ applications that run natively on Window
Using Trolltech s Qt you can build industrial-strength C++ applications that run natively on
Windows, Linux/Unix, Mac OS X, and embedded Linux--without making source code changes. With
this book Trolltech insiders have written a start-to-finish guide to getting great results with the most
powerful v ...
数据结构 The running time of quicksort can be improved in practice by taking advantage of the fast running t
The running time of quicksort can be improved in practice by taking advantage of the fast
running time of insertion sort when its input is “nearly” sorted. When quicksort is called on a
subarray with fewer than k elements, let it simply return without sorting the subarray. After the
top-level call ...
技术资料 基于FPGA设计的sdram读写测试实验Verilog逻辑源码Quartus工程文件+文档说明 DR
基于FPGA设计的sdram读写测试实验Verilog逻辑源码Quartus工程文件+文档说明，DRAM选用海力士公司的 HY57V2562 型号,容量为的 256Mbit,采用了 54 引脚的TSOP 封装, 数据宽度都为 16 位, 工作电压为 3.3V,并丏采用同步接口方式所有的信号都是时钟信号。FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ps ...