搜索:entity
找到约 42 项符合「entity」的查询结果
结果 42
按分类筛选
https://www.eeworm.com/dl/624/205575.html
串口编程
addition/subtraction entity for the addition/subtraction unit
addition/subtraction entity for the addition/subtraction unit
https://www.eeworm.com/dl/633/373300.html
Java编程
简单的在线聊天系统 jsp javabean entity
简单的在线聊天系统 jsp javabean entity
https://www.eeworm.com/dl/510126.html
计算机相关
LINQ to SQL和Entity Framework对比与关联
LINQ to SQL和Entity Framework都是一种包含LINQ功能的对象关系映射技术。他们之间的本质区别在于EF对数据库架构和我们查询的类型实行了更好的解耦。使用EF,我们查询的对象不再是完全对应数据库架构的C#类,而是更高层的抽象:Entity Data Model。这为我们提供了额外的灵活性,但是在性能和简单性上 ...
https://www.eeworm.com/dl/663/141284.html
VHDL/FPGA/Verilog
Three-input Majority Voter -- The entity declaration is followed by three alternative architectures
Three-input Majority Voter
-- The entity declaration is followed by three alternative architectures which achieve the same functionality in different ways.
https://www.eeworm.com/dl/648/291005.html
单片机开发
BSDL Description for Top-Level Entity TMS320F2812 --
BSDL Description for Top-Level Entity TMS320F2812 --
https://www.eeworm.com/dl/644/291711.html
汇编语言
BSDL Description for Top-Level Entity TMS320F2812
BSDL Description for Top-Level Entity TMS320F2812
https://www.eeworm.com/dl/633/322820.html
Java编程
web开发经典案例shoppingcart的EJB实现其entity部分
web开发经典案例shoppingcart的EJB实现其entity部分
https://www.eeworm.com/dl/534/208269.html
其他
-- Booth Multiplier -- This file contains all the entity-architectures for a complete -- k-bit
-- Booth Multiplier
-- This file contains all the entity-architectures for a complete
-- k-bit x k-bit Booth multiplier.
-- the design makes use of the new shift operators available in the VHDL-93 std
-- this design passes the Synplify synthesis check
https://www.eeworm.com/dl/663/170598.html
VHDL/FPGA/Verilog
-- Booth Multiplier -- This file contains all the entity-architectures for a complete -- k-bit x k
-- Booth Multiplier
-- This file contains all the entity-architectures for a complete
-- k-bit x k-bit Booth multiplier.
-- the design makes use of the new shift operators available in the VHDL-93 std
-- this design passes the Synplify synthesis check
-- download from: www.fpga.c ...