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软件设计/软件工程 The purpose of this document is to present how to use the Timer for the generation of a PWM signal t
The purpose of this document is to present how to use the Timer for the generation of a PWM signal tunable in frequency and duty cycle. As an application example, this document is based on a basic “music” synthesizer through an external buzzer. Example code is also available in the it.
技术资料 Atmel产品的资料
■ High Performance, Low Power AVR® 8-Bit Microcontroller
■ Advanced RISC Architecture
–120 Powerful Instructions – Most Single
Clock Cycle Execution
–32 x 8 General Purpose Working Registers
–Fully Static Operation
数学计算 用汇编语言实现的PN码
用汇编语言实现的PN码，长度为9。。只需要8个cycle就可以出32bit。。效率很高。。和大家一起共享：）
VHDL/FPGA/Verilog This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone.
This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.
DSP编程 完成在tigersharc201平台上划分出多个heap的操作
完成在tigersharc201平台上划分出多个heap的操作，同时示例在多个heap之间切换时的方法，并做出各种内存下访问的cycle统计
单片机编程 CAT28LV64-64Kb CMOS并行EEPROM数据手
The CAT28LV64 is a low voltage, low power, CMOS Parallel EEPROM organized as 8K x 8−bits. It requires a simple interface for in−system programming. On−chip address and data latches, self−timed write cycle with auto−clear and VCC power up/down write protection eliminate ...
VHDL/FPGA/Verilog Simple I2C controller -- 1) No multimaster -- 2) No slave mode -- 3) No fifo s -- -- notes:
Simple I2C controller
-- 1) No multimaster
-- 2) No slave mode
-- 3) No fifo s
--
-- notes:
-- Every command is acknowledged. Do not set a new command before previous is acknowledged.
-- Dout is available 1 clock cycle later as cmd_ack
技术资料 01 Stanford PhD A differential carrier-phase navigation system combining GPS with low earth orbit sa
资料->【E】光盘论文->【E1】斯坦福博士论文->01 Stanford PhD A differential carrier-phase navigation system combining GPS with low earth orbit satellites for rapid resolution of integer cycle ambiguities MatthewRabinowitzThesis01.pdf
VHDL/FPGA/Verilog IDCT-M is a medium speed 1D IDCT core -- it can accept a continous stream of 12-bit input words at
IDCT-M is a medium speed 1D IDCT core
-- it can accept a continous stream of 12-bit input words at a rate of
-- 1 bit/ck cycle, operating at 50MHz speed, it can process MP@ML MPEG video
-- the core is 100％ synthesizable
教程资料 WP409利用Xilinx FPGA打造出高端比特精度和周期精度浮点DSP算法实现方案
WP409利用Xilinx FPGA打造出高端比特精度和周期精度浮点DSP算法实现方案：
High-Level Implementation of Bit- and Cycle-Accurate Floating-Point DSP Algorithms with Xilinx FPGAs