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VHDL/FPGA/Verilog // -- Mode: Verilog -- // Filename : wb_master.v // Description : Wishbone Master Behavorial //

// -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General ...

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文章/文档  The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general co

The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general control and data transfer communication between ICs. Some of the features of the I2C bus are: &#8226 Two signal lines, a serial data line (SDA) and a serial clock line (SCL), and ground are required. A ...

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通讯/手机编程  iic总线控制器VHDL实现 -- VHDL Source Files: i2c.vhd -- top level file i2c_control.vhd -- control

iic总线控制器VHDL实现 -- VHDL Source Files: i2c.vhd -- top level file i2c_control.vhd -- control function for the I2C master/slave shift.vhd -- shift register uc_interface.vhd -- uC interface function for an 8-bit 68000-like uC upcnt4.vhd -- 4-bit up counter i2c_timesim.vhd -- po ...

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其他  WLAN仿真－发送机 wlan No Comments 设置完系统参数后

WLAN仿真－发送机 wlan No Comments 设置完系统参数后，开始产生发送数据。 1. 产生随机的发送bit（tx_bits），这里不考虑信道编码。 2. QAM映射 3. 将数据映射到不同载波，形成OFDM符号 4. 产生pilot，并将pilot插入OFDM符号中 5. 加入dc和guard子载波 6. 进行ifft，将频域信号变到时域，并加入循环前缀 7. 对信号进行ove ...

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VHDL/FPGA/Verilog 16点FFT VHDL源程序

16点FFT VHDL源程序，The xFFT16 fast Fourier transform (FFT) Core computes a 16-point complex FFT. The input data is a vector of 16 complex values represented as 16-bit 2’s complement numbers – 16-bits for each of the real and imaginary component of a datum.

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其他书籍  The MIPS32&#174 4KEm&#8482 core from MIPS&#174 Technologies is a member of the MIPS32 4KE&#8482 proc

The MIPS32&#174 4KEm&#8482 core from MIPS&#174 Technologies is a member of the MIPS32 4KE&#8482 processor core family. It is a high-performance, low-power, 32-bit MIPS RISC core designed for custom system-on-silicon applications. The core is designed for semiconductor manufacturing companies, ASIC d ...

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VHDL/FPGA/Verilog VHDL语言实现的穿行通讯

VHDL语言实现的穿行通讯，可实现闭环操作，通讯过程中每个bit位采样3次，保证数据准确。

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VHDL/FPGA/Verilog DDR SDRAM控制器的VHDL源代码

DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O&#8482 features in the Virtex&#8482 -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Dig ...

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软件设计/软件工程  软件简介：HI-TECH PICC 是一款高效的C编译器

软件简介：HI-TECH PICC 是一款高效的C编译器，支持Microchip PICmicro 10/12/14/16/17系列控制器。是一款强劲的标准C编译器，完全遵守ISO/ANSI C，支持所有的数据类型包括24 and 32 bit IEEE 标准浮点类型。智能优化产生高质量的代码。属于第三方开发工具。能和MPLAB整合，内嵌开发环境（HI－TIDE）。 Hi-tech PICC Compi ...

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通讯编程文档  H.264/AVC, the result of the collaboration between the ISO/IEC Moving Picture Experts Group and the

H.264/AVC, the result of the collaboration between the ISO/IEC Moving Picture Experts Group and the ITU-T Video Coding Experts Group, is the latest standard for video coding. The goals of this standardization effort were enhanced compression efficiency, network friendly video representation for inte ...

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