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嵌入式综合 1-Wire总线主机
Abstract: Communication with 1-Wire slave devices requires a 1-Wire master. There are numerous ways to build a 1-Wire master (see reference design 4206, "Choosing the Right 1-Wire Master for Embedded Applications"). Thisdocument describes the DS1WM, a synthesizable 1-Wire master that can be implem ...
单片机开发 Debussy是NOVAS Software, Inc(思源科技)發展的HDL Debug & Analysis tool
Debussy是NOVAS Software, Inc(思源科技)發展的HDL Debug & Analysis tool，這套軟體主要不是用來跑模擬或看波形，它最強大的功能是：能夠在HDL source code、schematic diagram、waveform、state bubble diagram之間，即時做trace，協助工程師debug。
可能您會覺的：只要有simulator如ModelSim就可以做debug了，我何必再學 ...
VHDL/FPGA/Verilog IDCT-M is a medium speed 1D IDCT core -- it can accept a continous stream of 12-bit input words at
IDCT-M is a medium speed 1D IDCT core
-- it can accept a continous stream of 12-bit input words at a rate of
-- 1 bit/ck cycle, operating at 50MHz speed, it can process MP@ML MPEG video
-- the core is 100％ synthesizable
通讯/手机编程 Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL c
Turbo Decoder Release 0.3
* Double binary, DVB-RCS code
* Soft Output Viterbi Algorithm
* MyHDL cycle/bit accurate model
* Synthesizable VHDL model
VHDL/FPGA/Verilog Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols.
Hard-decision decoding scheme
Codeword length (n) : 31 symbols.
Message length (k) : 19 symbols.
Error correction capability (t) : 6 symbols
One symbol represents 5 bit.
Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1
Generator polynomial, g(x) = a^15 a^21*X + a^6*X^2 + a^15*X^3 + a^ ...
串口编程 一个简单的ＳＰＩ ＩＰ核
一个简单的ＳＰＩ ＩＰ核，SPI Core Specifications 可以从说明文档中找到！
The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchronous communication protocol ...
其他嵌入式/单片机内容 This lab exercise will introduce you to the AccelWare IP generators. AccelWare is a library of over
This lab exercise will introduce you to the AccelWare IP generators. AccelWare is a library of over fifty IP generators, available in the form of three toolkits that produce synthesizable MATLAB for common MATLAB built in and toolbox functions. Each generator offers macro and micro-architecture sele ...
其他书籍 可综合的Verilog语法（剑桥大学
可综合的Verilog语法（剑桥大学，影印）
Synthesizable Verilogsyntax and semantics
VHDL/FPGA/Verilog DDR SDRAM控制器的VHDL源代码
DDR SDRAM控制器的VHDL源代码，含详细设计文档。
The DDR, DCM, and SelectI/O&#8482 features in the Virtex&#8482 -II architecture make it the perfect
choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock
Manager (DCM) provides the required Delay Locked Loop (DLL), Dig ...