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网络  Atheros Communications AR6001 WLAN Driver for SDIO installation Read Me March 26,2007 (based on

Atheros Communications AR6001 WLAN Driver for SDIO installation Read Me March 26,2007 (based on k14 fw1.1) Windows CE Embedded CE 6.0 driver installation. 1. Unzip the installation file onto your system (called installation directory below) 2. Create an OS design or open an existing OS design in ...

https://www.eeworm.com/dl/635/359584.html

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Linux/Unix编程  Linux下的.wav文件播放示例

Linux下的.wav文件播放示例，装了QT的话先#qmake -project生成工程文件pcm.pro，然后 #qmake pcm.pro生成Makefile，然后 #make 最后 #./pcm 执行注意代码里面包括要播放的.wav文件的路径

https://www.eeworm.com/dl/619/364731.html

下载: 87

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Linux/Unix编程  ELinks is an advanced and well-established feature-rich text mode web (HTTP/FTP/..) browser. ELinks

ELinks is an advanced and well-established feature-rich text mode web (HTTP/FTP/..) browser. ELinks can render both frames and tables, is highly customizable and can be extended via Lua or Guile scripts. It is quite portable and runs on a variety of platforms. Check the about page for a more complet ...

https://www.eeworm.com/dl/619/368572.html

下载: 97

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VHDL/FPGA/Verilog 秒表可计时

秒表可计时，用VHDL编译的源代码，从0.1到60秒计时，解压后直接用Quartus打开project即可

https://www.eeworm.com/dl/663/371614.html

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VHDL/FPGA/Verilog 用VHDL编译的源代码

用VHDL编译的源代码，模仿心脏跳动，解压后直接用Quartus打开project即可

https://www.eeworm.com/dl/663/371615.html

下载: 96

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VHDL/FPGA/Verilog 用VHDL编译的源代码

用VHDL编译的源代码，可编程脉冲生成器，解压后直接用Quartus打开project即可

https://www.eeworm.com/dl/663/371616.html

下载: 171

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VHDL/FPGA/Verilog 用VHDL编译的源代码

用VHDL编译的源代码，模拟心脏跳动，解压后直接用Quartus打开project即可，不好意思刚才第一个那个模拟心脏跳动（heartbeat）的源程序发错了，请删除，

https://www.eeworm.com/dl/663/371617.html

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VHDL/FPGA/Verilog 用VHDL编译的源代码

用VHDL编译的源代码，4bit加一器，输入一个4位二进制数自动加一，解压后直接用Quartus打开project即可

https://www.eeworm.com/dl/663/371618.html

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VHDL/FPGA/Verilog 用VHDL编译的源代码

用VHDL编译的源代码，两位优先级编码器，输入一个十进制数，直接显示头两个‘1’所在的位，解压后直接用Quartus打开project即可

https://www.eeworm.com/dl/663/371619.html

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DSP编程  DaVinci HD CPLD Firmware Resources 这是TI原装开发板DM6467原理图的 CPLD的VHDL代码

DaVinci HD CPLD Firmware Resources 这是TI原装开发板DM6467原理图的 CPLD的VHDL代码，是Spectrum Digital, Inc刚开发出来的！ CPLD Firmware Project CPLD Firmware Project (Version 6).

https://www.eeworm.com/dl/516/371662.html

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网络  Atheros Communications AR6001 WLAN Driver for SDIO installation Read Me March 26,2007 (based on

Linux/Unix编程  Linux下的.wav文件播放示例

Linux/Unix编程  ELinks is an advanced and well-established feature-rich text mode web (HTTP/FTP/..) browser. ELinks

VHDL/FPGA/Verilog 秒表可计时

VHDL/FPGA/Verilog 用VHDL编译的源代码

VHDL/FPGA/Verilog 用VHDL编译的源代码

VHDL/FPGA/Verilog 用VHDL编译的源代码

VHDL/FPGA/Verilog 用VHDL编译的源代码

VHDL/FPGA/Verilog 用VHDL编译的源代码

DSP编程  DaVinci HD CPLD Firmware Resources 这是TI原装开发板DM6467原理图的 CPLD的VHDL代码