搜索：PLL - 虫虫下载站

通讯/手机编程  Jitter is extremely important in systems using PLL-based clock drivers. The effects of jitter range

Jitter is extremely important in systems using PLL-based clock drivers. The effects of jitter range from not having any effect on system operation to rendering the system completely non-functional. This application note provides the reader with a clear understanding of jitter in high-speed systems. ...

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单片机开发  tenx radio pll ic tr1002 and radio ic ta2111 and refence code .

tenx radio pll ic tr1002 and radio ic ta2111 and refence code .

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radio and refence tenx

其他嵌入式/单片机内容  ADUC842 C程序集,包括ADC,DAC,PLL,PWM,WDT等程序．

ADUC842 C程序集,包括ADC,DAC,PLL,PWM,WDT等程序．

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ADUC 842 ADC DAC

系统设计方案  A new PLL topology and a new simplified linear model are presented. The new fractional-N synthesizer

A new PLL topology and a new simplified linear model are presented. The new fractional-N synthesizer presents no reference spurs and lowers the overall phase noise, thanks to the presence of a SampleJHold block. With a new simulation methodology it is possible to perform very accurate simulations, w ...

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new fractional-N synthesizer simplified

VHDL/FPGA/Verilog PLL 时钟模块　　Quartus II平台的简单设计实例　附仿真波形

PLL 时钟模块　　Quartus II平台的简单设计实例　附仿真波形

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Quartus PLL 时钟模块仿真

VHDL/FPGA/Verilog 基于FPGA和PLL的函数信号发生器时钟部分的实现

基于FPGA和PLL的函数信号发生器时钟部分的实现

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FPGA PLL 函数信号发生器时钟

电子技术  PLL电路的研究及在信号产生中的应用论文资料

0114、PLL电路的研究及在信号产生中的应用论文资料

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电子书籍  最全面最权威的锁相环PLL原理与应用资料.rar

锁相技术相关专辑 38册 209M最全面最权威的锁相环PLL原理与应用资料.rar

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技术资料  DSP内嵌PLL中的CMOS压控环形振荡器设计

·摘要：&nbsp; 介绍了一种用于DSP内嵌锁相环的低功耗、高线性CMOS压控环形振荡器.电路采用四级延迟单元来获得相位相差90.的正交输出时钟,每级采用调节电流源大小,改变电容放电速度的方式.基于SMIC 0.35μm CMOS工艺模型的仿真结果表明,电路可实现2MHz至90MHz的频率调节范围,在中心频率附近具有很高的调节线性度,且总功耗仅 ...

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CMOS

微处理器开发  Excel spreadsheet allowing calculation of the best R-C-C component values on the PLL Loop Back Filte

Excel spreadsheet allowing calculation of the best R-C-C component values on the PLL Loop Back Filter.

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spreadsheet calculation component the

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