搜索：PLB
找到约 15 项符合「PLB」的查询结果
结果 15
https://www.eeworm.com/dl/fpga/doc/32604.html
教程资料
PLB Block RAM(BRAM)接口控制器
The PLB BRAM Interface Controller is a module thatattaches to the PLB (Processor Local Bus).
https://www.eeworm.com/dl/kbcluoji/40084.html
可编程逻辑
PLB Block RAM(BRAM)接口控制器
The PLB BRAM Interface Controller is a module thatattaches to the PLB (Processor Local Bus).
https://www.eeworm.com/dl/564/33745.html
通信网络
带有SerDes接口的PLB千兆位级以太网MAC
This application note describes a reference system which illustrates how to build an embeddedPowerPC® system using the Xilinx 1-Gigabit Ethernet Media Access Controller processor core.This system has the PLB_Gemac configured to use Scatter/Gather Direct Memory Access andthe ...
https://www.eeworm.com/dl/930581.html
技术资料
基于流水线负载平衡模型的并行爬虫研究
针对并行爬虫系统在多任务并发执行时所遇到的模块间负载平衡问题，提出流水线负载平衡模型(PLB)，将不同的任务抽象为独立模块而达到各模块的处理速度相等，采用多线程的方式实现基于PLB的并行爬虫，根据线程 ...
https://www.eeworm.com/dl/663/489313.html
VHDL/FPGA/Verilog
Here an embedded System-on-Chip is build, in an Xilinx Spartan-3 FPGA with Microblaze as the process
Here an embedded System-on-Chip is build, in an Xilinx Spartan-3 FPGA with Microblaze as the processor.A PLB core System is made with the VGA IP core attached to it. The software written for the MicroBlaze processor specifies the object, the color and the movement of the display. ...
https://www.eeworm.com/dl/684/266335.html
软件设计/软件工程
SDRAM 参考设计:主要包括The following figure shows a high-level block diagram for this reference design follo
SDRAM 参考设计:主要包括The following figure shows a high-level block diagram for this reference design followed by a brief
description of each sub-section. The design consists of:
· PowerPC processor
· PLB-OPB bridge
· BlockRAM Memory Controller
· SDRAM Controller
· Two GPIO ...