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单片机编程 基于89C51的摄像机镜头控制电路设计

针对视频监控中摄像机镜头光圈大小、图像聚焦、图像变焦三项参数的控制问题，介绍了一种基于89C51单片机的镜头控制电路的设计。 该电路以89C51单片机为核心，结构简单，成本低廉，控制可靠，实现了智能监控终端对摄像参数的完全控制。 Abstract:  The design of camera lens control circuit based on 89C51 is int ...
https://www.eeworm.com/dl/502/29337.html
下载: 131
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单片机编程 基于P87C591的信号采集节点的设计

介绍了CAN总线和P87C591单片机的特点，给出了基于P87C591单片机的信号采集节点的软、硬件设计，指出了硬件电路设计中应注意的问题，在软件设计中重点介绍了节点初始化、报文发送和报文接收等子程序。 Abstract:  The features of CAN Bus and the microcontroller P87C591 are introduced, and the design of hardw ...
https://www.eeworm.com/dl/502/29345.html
下载: 103
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教程资料 《器件封装用户向导》赛灵思产品封装资料

Introduction to Xilinx Packaging Electronic packages are interconnectable housings for semiconductor devices. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat generated by the device. Feature sizes a ...
https://www.eeworm.com/dl/fpga/doc/32374.html
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无线通信 CF卡技术资料

The information in this specification is subject to change without notice.Use of this specification for product design requires an executed license agreement from the CompactFlashAssociation.The CompactFlash Association shall not be liable for technical or editorial errors or omissions contained her ...
https://www.eeworm.com/dl/510/36525.html
下载: 100
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可编程逻辑 《器件封装用户向导》赛灵思产品封装资料

Introduction to Xilinx Packaging Electronic packages are interconnectable housings for semiconductor devices. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat generated by the device. Feature sizes a ...
https://www.eeworm.com/dl/kbcluoji/39540.html
下载: 33
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可编程逻辑 XAPP708 -133MHz PCI-X到128MB DDR小型DIMM存储器桥

  The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Spec ...
https://www.eeworm.com/dl/kbcluoji/40099.html
下载: 131
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数据库系统 摘要 　?　?　?　?　　 　　设计时的自动化加快了编码

摘要 　?　?　?　?　　 　　设计时的自动化加快了编码，并保证所有过程都用相同的命名规范和结构来生成。为了在大型 SQL 项目中尽量提高编码的效率，作者编写了一系列的设计时（design-time）存储过程，用它们来生成运行时（run-time）存储过程，并一直在工程中使用。最近，作者更新了其存储过程以便使用 SQL Server 2000 ...
https://www.eeworm.com/dl/523/103340.html
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其他 国外的人才求职招聘最新版

国外的人才求职招聘最新版，找了很久的，还在调试中，旧版本说明如下PHP写的一个人力资源管理系统的源码：系统采用模块话的设计，此文件解压到php的环境下，直接访问就可以，需要建立一个mysql数据库数据库名为orangeHRM，并建立一个用户。然后直接访问http：//localhost/orangehrm就ok！-PHP write a human resources mana ...
https://www.eeworm.com/dl/534/341450.html
下载: 161
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VHDL/FPGA/Verilog Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH

Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift ...
https://www.eeworm.com/dl/663/361747.html
下载: 164
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VHDL/FPGA/Verilog Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH

Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift ...
https://www.eeworm.com/dl/663/361749.html
下载: 129
查看: 1075