搜索：IP技术 - 虫虫下载站

VHDL/FPGA/Verilog HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptiv

HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP core is licensed under MIT License

https://www.eeworm.com/dl/663/457421.html

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其他数据库  使用PB实现取得多网卡ip GetIP支持多网卡

使用PB实现取得多网卡ip GetIP支持多网卡

https://www.eeworm.com/dl/645/457422.html

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GetIP 多网

VHDL/FPGA/Verilog This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone.

This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.

https://www.eeworm.com/dl/663/457520.html

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Tensilica OpenCores interface the

嵌入式Linux IP电话GUI界面设计及源代码,应用参考.

IP电话GUI界面设计及源代码,应用参考.

https://www.eeworm.com/dl/653/459842.html

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GUI IP电话界面设计源代码

VHDL/FPGA/Verilog Alera 的8051 IP core的示例文件5个

Alera 的8051 IP core的示例文件5个

https://www.eeworm.com/dl/663/463246.html

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Alera 8051 core IP

嵌入式/单片机编程  嵌入式tcp-ip协议栈。。。。。。阿萨德

嵌入式tcp-ip协议栈。。。。。。阿萨德

https://www.eeworm.com/dl/647/466859.html

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tcp-ip 嵌入式协议栈

Linux/Unix编程  linux下的tcp/ip协议实现的确部分阅读笔记

linux下的tcp/ip协议实现的确部分阅读笔记

https://www.eeworm.com/dl/619/466936.html

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linux tcp ip 协议

VHDL/FPGA/Verilog Avalon总线下的PWM的IP模块。基于VHDL语言。

Avalon总线下的PWM的IP模块。基于VHDL语言。

https://www.eeworm.com/dl/663/468062.html

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Avalon VHDL PWM 总线

uCOS 包含lwip这个精简IP协议栈的ucos源代码

包含lwip这个精简IP协议栈的ucos源代码

https://www.eeworm.com/dl/649/480093.html

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lwip ucos IP协议栈

Linux/Unix编程  The Linux TCP/IP Stack: Networking for Embedded Systems by Thomas F. Herbert

The Linux TCP/IP Stack: Networking for Embedded Systems by Thomas F. Herbert

https://www.eeworm.com/dl/619/482838.html

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F. Networking Embedded Herbert

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