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其他书籍 This paper examines the asymptotic (large sample) performance of a family of non-data aided feedfor
This paper examines the asymptotic (large sample) performance
of a family of non-data aided feedforward (NDA FF) nonlinear
least-squares (NLS) type carrier frequency estimators for burst-mode
phase shift keying (PSK) modulations transmitted through AWGN and
flat Ricean-fading channels. The asymptoti ...
电子书籍 S29NS-J 128 Megabit (8 M x 16-Bit), 64 Megabit (4 M x 16-Bit), 32 Megabit (2 M x 16-Bit), and 16
S29NS-J
128 Megabit (8 M x 16-Bit), 64 Megabit (4 M x 16-Bit),
32 Megabit (2 M x 16-Bit), and 16 Megabit (1 M x 16 Bit),
110 nm CMOS 1.8-Volt only Simultaneous Read/Write,
Burst Mode Flash Memories
Data Sheet
系统设计方案 自相似、长相关业务的生成及TCP拥塞控制的研究 目前,Internet的规模日益增大,承载的业务种类也不断增加.Internet已给人们的生活和工作带来了巨大的利益和影响.21世纪是通信的世纪,是互
自相似、长相关业务的生成及TCP拥塞控制的研究
目前,Internet的规模日益增大,承载的业务种类也不断增加.Internet已给人们的生活和工作带来了巨大的利益和影响.21世纪是通信的世纪,是互连网的世纪.经过20多年的发展,Internet已经在全球取得巨大的成功.该文对自相似、长相关基本理论进行了研究,得出了生成自相似、长相关业务 ...
VHDL/FPGA/Verilog This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone.
This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.
源码 CC2520+STM32
#define RF_CHANNEL                25      // 2.4 GHz RF channel
// BasicRF address definitions   µØÖ·¶¨Òå
#define PAN_ID               0x2007
#define TX_ADDR           &nb ...
书籍 Mobile Cloud Computing Systems
There is a phenomenal burst of research activities in mobile cloud
computing systems, which extends cloud computing functions, ser-
vices, and results to the world of future mobile communications
applications, and the paradigm of cloud computing and virtualization
to mobile networks. Mobile applicat ...
技术资料 基于FPGA设计的sdram读写测试实验Verilog逻辑源码Quartus工程文件+文档说明 DR
基于FPGA设计的sdram读写测试实验Verilog逻辑源码Quartus工程文件+文档说明，DRAM选用海力士公司的 HY57V2562 型号,容量为的 256Mbit,采用了 54 引脚的TSOP 封装, 数据宽度都为 16 位, 工作电压为 3.3V,并丏采用同步接口方式所有的信号都是时钟信号。FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ps ...
技术资料 DDR4标准 JESD79_4
1. Scope ......................................................................................................................................................................... 12. DDR4 SDRAM Package Pinout and Addressing ............................................................................ ...