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VHDL/FPGA/Verilog vhdl编写

vhdl编写，8b—10b 编解码器设计 Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all logic Encoded data output ...

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vhdl 编写

VHDL/FPGA/Verilog VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register betw

VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- s ...

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SPI bus register effect

串口编程  CHAPT14MODEM.CPP Implementation of the Modem class CHAPT14MODEM.H Declarations of the Modem class

CHAPT14\MODEM.CPP Implementation of the Modem class CHAPT14\MODEM.H Declarations of the Modem class CHAPT14\TSTMODEM.CPP 16-bit test program for the Modem class CHAPT14\TSTMODEM.EXE 16-bit executable of the test program CHAPT14\TSTMODEM.MAK Make file for use with Borland or Microsoft C

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CHAPT MODEM Modem class

源码  源代码LIBRARY IEEE USE IEEE

通用寄存器的部分代码 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY traffic IS PORT(clk,sm,sb:IN bit mr,my,mg,br,by,bg:OUT bit ) END traffic

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IEEE LIBRARY USE 源代码

matlab例程  This program includes: [5 7] convolutional code (encoder) + BPSK + AWGN + MAP (decoder). It evaluat

This program includes: [5 7] convolutional code (encoder) + BPSK + AWGN + MAP (decoder). It evaluates Bit Error Rate and plots it versus SNR(signal to Noise Ratio).

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convolutional includes program encoder

驱动编程  The DiskPerf filter driver monitors disk-accesses, capturing performance data. It supports Plug and

The DiskPerf filter driver monitors disk-accesses, capturing performance data. It supports Plug and Play, Power Management, and WMI . It is not 64-bit compliant

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disk-accesses performance capturing DiskPerf

VHDL/FPGA/Verilog 用verilog语言编写

用verilog语言编写，一个8-bit ALU，可以完成按字节的+、-和与、或、非操作

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verilog 语言编写

技术资料  DIMM Module Using PI74SSTV16857 Register and PI6CV857 PLL Clock Driver

The PI74SSTV16857 is a 14-bit stub-series-terminated logic (SSTL_2)registered driver with dif

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Register Module Driver

技术资料  M68040用户手册(附录B)

The MC68EC040 is Motorola's third generation of M68000-compatible, high-performance,32-bit micro

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M68040 用户手册

技术资料  4034 CMOS 8位双向并、串入、并出寄存器

The CD4034BM/CD4034BC is an 8-bit CMOS static shiftregister with two parallel bidirectional d

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4034 CMOS

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