sec_counter.v

verilog代码集锦.rar

module sec_counter(clock,reset,load,din,count);
      input clock,reset,load;
      input[5:0]din;
      output [5:0]count;
      reg [5:0]count;
      always@(posedge clock or posedge reset)begin
            if(reset) count<=0;
            else begin
               if(load)count<=din;
               else count<=(count==59)?0:(count+1);
            end      
      end
endmodule

`timescale 1ns/1ns
module sec_counter_tb;
 reg clock,reset,load;
 reg[5:0]din;
 wire[5:0]count;
 
 always # 1 clock=~clock;
 sec_counter c1(.clock(clock),.reset(reset),.load(load),.din(din),.count(count));
 initial begin
    clock=0;
    reset=0;
    load=0;
    din=6'd8;
    #4 reset=1;
    #4 reset=0;
    #4 load=1;
    #4 load=0;
    $monitor("At time%t,count=%b",$time,count);
    #1000$stop;
  end 
 endmodule