shift.v

verilog代码集锦.rar

module shift(data_out,data_in,rst_,clk);
    output[3:0]data_out;
    input data_in;
    input rst_;
    input clk;
    reg[3:0]data_out;
    always@(posedge clk or negedge rst_)
          if(!rst_)
          	 data_out<=4'b0;
          else 
          	 data_out<={data_out[2:0],data_in};
  	
endmodule
`timescale 1ns/1ns
module shift_tb;
    reg data_in;
    reg rst_,clk;
    wire [3:0]data_out;
    
    always #1 clk=~clk;
    initial begin
       rst_=1;
       clk=0;
       #6 rst_=0;
       data_in=1'b1;
       #2 rst_=1;
       #10 data_in=1'b0;     
       #100$stop;
    end
always@(posedge clk)
       $monitor ("At time%t,data_out=%b",$time,data_out);    
shift c1(.data_out(data_out),.data_in(data_in),.rst_(rst_),.clk(clk));
endmodule