five_divider.v

verilog代码集锦.rar

//*************************************
//   file name :five_divider
//      author :yilong.you
//        date :October 12,2008 
//*************************************



module five_divider(  clk,
                      reset,
                      clk_out  );
    input   clk     ;//input clk
    input   reset   ;//input reset
    output  clk_out ;//output clk
    
    reg [2:0]i,j;
    reg clk1,clk2;
    
    assign clk_out=clk1|clk2;
    always@(posedge clk or negedge reset)begin
          if(!reset)begin
              clk1<=0;
              i<=0;
          end
          else if(i==3)begin
              clk1<=~clk1;
              i<=i+1; 
            end
          
          else if(i==5)begin
              clk1<=~clk1;
              i<=1;
          end 
          
          else i<=i+1;
         
    end
    
   always@(negedge clk or negedge reset)begin
          if(!reset)begin
              clk2<=0;
              j<=0;
          end
          else if(j==3)begin
              clk2<=~clk2;
              j<=j+1; 
            end
          
          else if(j==5)begin
              clk2<=~clk2;
              j<=1;
          end 
  
          
          else j<=j+1;
         
  end
 endmodule
 
 `timescale 1ns/1ns
 module five_divider_tb;
     reg clk,reset;
     wire clk_out;
     
     always #1 clk=~clk;
     initial begin
           clk=0;
           reset=1;
        #1 reset=0;
        #2 reset=1;
        #100$stop;
     end
     
     five_divider c1(.clk(clk),.reset(reset),.clk_out(clk_out));
 endmodule