lfsr_updown.v
来自「verilog代码集锦.rar」· Verilog 代码 · 共 38 行
V
38 行
`define WIDTH 8module lfsr_updown(clk, //Clock inputreset, //Reset inputenable, //Enable inputup_down, //Up Down inputcount, //Count outputoverflow //Overflow output);input clk;input reset;input enable;input up_down;output[`WIDTH-1:0]count;output overflow;reg[`WIDTH-1:0]count;assign overflow=(up_down)?(count=={{`WIDTH-1{1'b0}},1'b1}):(count=={1'b1,{`WIDTH-1{1'b0}}});always@(posedge clk)if(reset) count<={`WIDTH{1'b0}};else if(enable)begin if(up_down)begin count<={~(^count&`WIDTH'b01100011),count[`WIDTH-1:1]}; end else begin count<={count[`WIDTH-2:0],~(^(count&`WIDTH'b10110001))}; endendendmodule
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