myrom_tb.v

来自「verilog代码集锦.rar」· Verilog 代码 · 共 22 行

`timescale 1ns/10ps
module myrom_tb;
reg read_en_;
reg [3:0]addr;
wire [3:0]read_data;

myrom c1(.read_data(read_data),.addr(addr),.read_en_(read_en_));
initial begin
   read_en_=1;
   #5 read_en_=0;
   #5 read_en_=1;
end

initial begin:ONCE
  reg [4:0]pa;
  for(pa=0;pa<16;pa=pa+1)begin
      addr=pa;
    $display("%b",read_data);
  end
 
end
endmodule