decode4_7.v

verilog代码集锦.rar

module decode4_7(decodeout,indec);
       input [3:0]indec;
       output [6:0] decodeout;
       reg [6:0] decodeout;
       
       always@(indec)
          begin
             case(indec)
             4'b0000: decodeout = 7'b1000000; // 0
				     4'b0001: decodeout = 7'b1111001; // 1
				     4'b0010: decodeout = 7'b0100100; // 2
				     4'b0011: decodeout = 7'b0110000; // 3
				     4'b0100: decodeout = 7'b0011001; // 4
				     4'b0101: decodeout = 7'b0010010; // 5
				     4'b0110: decodeout = 7'b0000011; // 6
				     4'b0111: decodeout = 7'b1111000; // 7
				     4'b1000: decodeout = 7'b0000000; // 8
				     4'b1001: decodeout = 7'b0011000; // 9
             default:decodeout=7'bz;
             endcase
          end
endmodule
        
`timescale 1ns/1ns
module tb_decode4_7;
  reg[3:0]indec;
  wire [6:0] decodeout;
  initial begin:OK
     reg [4:0]pa;
     for(pa=0;pa<10;pa=pa+1)begin
       indec=pa;    
     #1 $display("indec=%b.decodeout=%b",indec,decodeout);  
    end
  end        
  decode4_7 c1(.decodeout(decodeout),.indec(indec));
endmodule