fenpin2.v

verilog代码集锦.rar

module fenpin2(clk,reset,clk_out);
  input clk,reset;
  output clk_out;
  wire clk_tmp1;
  reg clk_tmp2,clk_tmp;
  reg [2:0]count;
  
  assign clk_tmp1=clk^clk_tmp2;
  assign clk_out=clk_tmp;
  
  always@(posedge clk_tmp1 or posedge reset)begin
     if(reset)begin
       clk_tmp2<=0;
       count<=3'b010;
     end
     
    else if(count==3'b000)
    	       count <=3'b010;
    else
    	 	 count<=count-1;
  
  end
  
  always@(posedge clk_tmp1)begin
       if(count==3'b001)
       	 clk_tmp<=1'b1;
       else
       	 clk_tmp<=1'b0;	
  end
                  
  always@(posedge clk_tmp)begin
        clk_tmp2<=!clk_tmp2;
  end
endmodule

`timescale 1ns/1ns
module fenpin2_tb;
reg clk,reset;
wire clk_out;

always #1 clk=~clk;
initial begin
	clk=0;
	reset=0;
	#2 reset=1;
	#2 reset=0;
	#100$stop;
end  	 
fenpin2 c1(.clk(clk),.reset(reset),.clk_out(clk_out));
endmodule