dividern_5.v

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//-----------------------------------------------------------
//  file name: N-5 divider
//     author: Yilong.you
//       date: October 14,2008
//----------------------------------------------------------

module dividerN_5(  clk_in    ,
                    reset     ,
                    clk_out
                            ) ;      //port list
       input     clk_in ;      
       input     reset  ;       
       output    clk_out;            //port declaration
       
       parameter N=6;
       
       reg clk_tmp;                 //the input clk we really need 
       
       
       reg clk_out;
       reg sel;                      //the control signal to select the needed clk
       reg[2:0]count;
       
     
       
       initial sel=0;
       always @(sel)
           if(sel==1)clk_tmp=~clk_tmp;
           else clk_tmp=clk_in;
      
       
       always@(posedge clk_tmp)begin
          if(reset)begin
             count<=0;
             clk_out<=0;
          end
          else begin
             if(count==N-2)begin
                sel<=1;
                count<=count+1;
             end
             
             else if(count==N)begin
             	  //sel<=0;
                clk_out<=~clk_out;
                count<=count+1;  
             end
             
             else if(count==N+1)begin
                clk_out<=~clk_out;
                count<=1;
             end
             else count<=count+1;
          end 
       end
endmodule
         
`timescale 1ns/1ns
module tb_dividerN_5;
       reg   clk_in ;
       reg   reset  ;
       wire  clk_out;
       
       dividerN_5 c1(.clk_in(clk_in),.reset(reset),.clk_out(clk_out));
       
       always #1 clk_in=~clk_in;
       initial begin
       	    clk_in=0;
            reset =0;
         #2 reset =1;
         #2 reset =0;
         #100 $stop ;     
       end      
endmodule