multiply_tb.v

来自「verilog代码集锦.rar」· Verilog 代码 · 共 24 行

module Multiply_tb;
	reg [7:0]Mplr,Mcnd;
	reg Clock,Reset;
	wire Done;
	wire[15:0]Acc;
	
	always #5 Clock=~Clock;
	initial begin
		Clock=0;
		Reset=1;
		#30 Reset=0;	
		//Mplr=8'b11010011;
		//Mcnd=8'b10101111;		
		repeat(5)begin		    
			#170  Mplr={$random}%256;
			      Mcnd={$random}%256;			  
	   	$display("Mplr=%b---Mcnd=%b---Acc=%b,Done=%b",Mplr,Mcnd,Acc,Done);
      end  	 
		#10000$stop;
	end
	
	Multiply c1(.Mplr(Mplr),.Mcnd(Mcnd),.Clock(Clock),.Reset(Reset),.Done(Done),.Acc(Acc));
endmodule