wave.v

verilog代码集锦.rar

module wave(clk,reset,clk1);
  input clk,reset;
  output clk1;
  reg clk1;
  reg [1:0]i;
always@(posedge clk or negedge reset)
   if(!reset)begin
   	  clk1<=0;
   	  i<=0;
   end
   
   else begin
   	       
   	        if(i==2)begin
  		          clk1<=~clk1;
  		          i<=i+1;
            end
    
            else if(i==3)begin
    	          clk1<=~clk1;
    	          i<=1;
            end
    
            else i<=i+1;
   end
  endmodule
  
  `timescale 1ns/1ns
module wave_tb;
reg clk,reset;
wire clk1;

always #1 clk=~clk;
initial begin
	clk=0;
	reset=1;
	#1 reset=0;
	#2 reset=1;
	#100$stop;
end  	 
wave c1(.clk(clk),.reset(reset),.clk1(clk1));
endmodule