parity_check.v
来自「verilog代码集锦.rar」· Verilog 代码 · 共 32 行
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32 行
module Parity_Check;reg [0:7] a;reg s;initial begin a=8'b11000111; endfunction Parity; input [0:7] Set; //output Parity; //reg Parity; reg[0:2] Ret; integer j; begin Ret=0; for(j=0;j<8;j=j+1)begin if(Set[j]==1) Ret=Ret+1; end Parity=Ret%2; endendfunctioninitial begin s=Parity(a); $display("a=%b,s=%b",a,s);end endmodule
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