adder4.v

来自「verilog代码集锦.rar」· Verilog 代码 · 共 35 行

module adder4(cout,sum,ina,inb,cin);
   output [3:0] sum;
   output cout;
   input  [3:0] ina,inb;
   input cin;
   assign{cout,sum}=ina+inb+cin;
endmodule


`timescale 1ns/1ns
module tb_adder4;
 reg [3:0] ina;
 reg [3:0] inb;
 reg cin;
 wire [3:0] sum;
 wire cout;
 
 adder4 c1(.cout(cout),.sum(sum),.ina(ina),.inb(inb),.cin(cin));
 initial begin:ONCE
    cin=0;ina=0;inb=0;
    repeat(2)begin
       #20 ina={$random}%16;
           inb={$random}%16;
    end
    
    cin=1;ina=0;inb=0;
    repeat(2)begin
      #20 ina={$random}%16;
          inb={$random}%16;
    end
    $monitor("At time%t,ina=%b,inb=%b,sum=%b,cout=%b",$realtime,ina,inb,sum,cout);
 end
endmodule