rever_clk.v

来自「verilog代码集锦.rar」· Verilog 代码 · 共 21 行

module rever_clk(clk,clk_out);
   input clk;
   output clk_out;
   
   xor u1(clk_out,clk,1'b1);
   
endmodule

`timescale 1ns/1ns
module rever_clk_tb;
  reg clk;
  wire clk_out;

   always #1 clk=~clk;
   rever_clk c1(.clk(clk),.clk_out(clk_out));
   initial begin
     clk=0;
     # 50 $stop;
   end
endmodule