global_var.v
来自「verilog代码集锦.rar」· Verilog 代码 · 共 27 行
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module Global_Var;reg[0:7] RamQ[0:63];integer index;reg CheckBit;initial begin for (index=0;index<=63;index=index+1) RamQ[index]={$random}%256; end task GetParity; input Address; output ParityBit; ParityBit=^RamQ[Address];endtask initial for (index=0;index<=63;index=index+1) begin GetParity(index,CheckBit); $display("Parity bit of memory word %d is %b",index,CheckBit); end endmodule
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