tb_bcdcount60.v

来自「verilog代码集锦.rar」· Verilog 代码 · 共 25 行

module tb_BCDcount60;
    reg load,cin,clk,reset;
    reg [7:0] data;
    wire [7:0] qout;
    wire cout;
    
    always #1 clk=~clk;
    
    BCDcount60  c1(.qout(qout),.cout(cout),.data(data),.load(load),.cin(cin),.reset(reset),.clk(clk));
    
    initial begin
       data=8'b00010110;
       clk=0;
       reset=1;
       cin=0;
       #4 reset=0;
          load=1;
       #4 load=0;
          cin=1;
       #100 $stop;
       $monitor("at time %t",$time,"qout[7:4]=%b,qout[3:0]=%b,cout=%b",qout[7:4],qout[3:0],cout);   
            
    end
endmodule