wave2.v
来自「verilog代码集锦.rar」· Verilog 代码 · 共 16 行
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16 行
`timescale 10ns/1nsmodule wave2;reg wave;parameter cycle=5;initial fork wave=0; #(cycle) wave=1; #(2*cycle) wave=0; #(3*cycle) wave=1; #(4*cycle) wave=0; #(5*cycle) wave=1; joininitial $monitor($time,"wave=%b",wave);endmodule
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