has_task.v

verilog代码集锦.rar

module Has_Task;
   parameter MAXBITS=8;
   task Revers_Bits;
       input [MAXBITS-1:0]Din;
       output [MAXBITS-1:0]Dout;l
       integer k;
       begin
          for(k=0;k<MAXBIST;k=k+1)
          Dout[MAXBIST-1-k]=Din[k];
       end
   endtask
   endmodule