myrom.v

verilog代码集锦.rar

`timescale 1ns/10ps
module myrom(read_data,addr,read_en_);
input read_en_;
input[3:0]addr;
output [3:0]read_data;

reg [3:0]read_data;
reg[3:0]mem[0:15];

initial 
 $readmemb("my_rom_data",mem);
always@(addr or read_en_)
   if(!read_en_)
      read_data=mem[addr];
endmodule