traffic_light_controller2.v
来自「verilog代码集锦.rar」· Verilog 代码 · 共 56 行
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56 行
//***************************************************// File Name: traffic_light_controller.v// Date: October7,2008// author: yilong.you// yilong.you@stu.xjtu.edu.cn //**************************************************/module traffic_light_controller2(clk,reset,light_color); input clk,reset; output[1:0] light_color; reg[1:0] light_color,state; reg[5:0]count; parameter S0=2'd0,green=2'd1,yellow=2'd2,red=2'd3; initial state=S0; always@(posedge clk or posedge reset)begin if(reset)begin state<=S0; count<=0; end else case(state) S0: state<=green; green: begin count<=count+1; if(count==24) state<=yellow; end yellow:begin count<=count+1; if(count==26) state<=red; end red: begin count<=count+1; if(count==41) state<=green; end default: count<=count+1; endcase end always@(negedge clk) light_color<=state;endmodule
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