instruction_memory.v

流水线CPU的Verilog代码.rar

module instruction_memory(clk, instruction, addr, read, enable); //it's a rom, output 4 sequential bytes beginning at address of addr
	input clk;
	input[31:0] addr;
	input read, enable;
	output reg [31:0] instruction;
	reg [7:0] memory[8'b11111111-1:0];
	
	initial
	   begin
	       {memory[3],memory[2],memory[1],memory[0]} = 32'b00000010010100111000100000100000;  //the instruction means: add $17, $18, $19 #$17 = $ 18 + $19
	   end
	
	always @(posedge clk)
		begin
			instruction[7:0] <= (read && enable) ? memory[addr] : 8'bzzzzzzzz;
			instruction[15:8] <= (read && enable) ? memory[addr+1] : 8'bzzzzzzzz;
			instruction[23:16] <= (read && enable) ? memory[addr+2] : 8'bzzzzzzzz;
			instruction[31:24] <= (read && enable) ? memory[addr+3] : 8'bzzzzzzzz;
		end
	
endmodule