instruction_fetch.v

流水线CPU的Verilog代码.rar

`timescale 1ns/10ps
module instruction_fetch(clk, reset, instruction, branch_bus, execution_destination, memory_destination, write_back_destination);
		input clk;
		input reset;
		output reg[31:0] instruction;
		input[33:0] branch_bus;	
		input[4:0] execution_destination, memory_destination, write_back_destination;
		
				
				
		reg[31:0] pc;
		wire fetch_instruction_enable = //handle data hazard
		((instruction[5:0] == 6'b100000 || instruction[5:0] == 6'b100010 || instruction[5:0] == 6'b100100 || instruction[5:0] == 6'b100101 || 
		instruction[5:0] == 6'b101010 || instruction[31:26] == 6'b101011 || instruction[31:26] == 6'b000100 || instruction[31:26] == 6'b000101) //add sub and or slt sw bne beq
									  && (instruction[20:16] == execution_destination && execution_destination != 0 ||
										  instruction[20:16] == memory_destination && memory_destination != 0 ||
										  instruction[20:16] == write_back_destination && write_back_destination != 0 ||
										  instruction[25:21] == execution_destination && execution_destination != 0 ||
										  instruction[25:21] == memory_destination && memory_destination != 0 ||
										  instruction[25:21] == write_back_destination && write_back_destination != 0) ||  
	   (instruction[31:26] == 6'b100011) && (instruction[25:21] == execution_destination && execution_destination != 0 ||      //lw
										  instruction[25:21] == memory_destination && memory_destination != 0 ||
										  instruction[25:21] == write_back_destination && write_back_destination != 0) ||
	   (instruction[31:26] == 6'b001000 || instruction[31:26] == 6'b001100 || instruction[31:26] == 6'b001101)                      //addi andi ori
	   								  && (instruction[25:21] == execution_destination && execution_destination != 0 ||      
										  instruction[25:21] == memory_destination && memory_destination != 0 ||
										  instruction[25:21] == write_back_destination && write_back_destination != 0) ||
	   (instruction[31:26] == 6'b000010)) ? 1'b0 : 1'b1;  //JUMP
       //13 instructions
       
       
       wire branch_bus_valid; 
       wire branch_bus_taken;
       wire[31:0] branch_bus_offset;
       
       assign branch_bus_valid = branch_bus[33];  
       assign branch_bus_taken = branch_bus[32];  
       assign branch_bus_offset = branch_bus[31:0];
 
	   wire[31:0] instruction_from_memory;
		
	   instruction_memory instruction_memory_instance(.clk(clk), .instruction(instruction_from_memory), .addr(pc), .read(1'b1),. enable(1'b1));      
       
       
       //-------------------------calculate PC first then fetch instruction------------------------------
       wire[31:0] pc_offset = ((branch_bus_valid && branch_bus_taken) ? branch_bus_offset : 4);
       
	   always @(posedge clk)
	   	begin 
	   		if(reset)
	   			begin
	   				pc <= -4;
       				instruction <= 32'h00000000;
       			end
			else
				if(fetch_instruction_enable)
					pc <= pc + pc_offset;
			
			if(!reset && fetch_instruction_enable)
				instruction <= instruction_from_memory;
		end

	
//	always @(negedge clk)
//		if(!reset && fetch_instruction_enable)
//			instruction = instruction_from_memory;
	
	
	//-------------------------------------------------------------------------------------------------
		
		
endmodule