execution.v

流水线CPU的Verilog代码.rar

`timescale 1ns/10ps

module execution(clk, reset, instruction_decode_bus, execution_bus, execution_destination);
	input clk;
	input reset;
	input[107:0] instruction_decode_bus;
	output[75:0] execution_bus;
	output[4:0] execution_destination;
	
	wire instruction_decode_bus_valid;
	wire[5:0] instruction_decode_bus_operation;
	wire[4:0] instruction_decode_bus_destination;
	wire[31:0] instruction_decode_bus_valueA;
	wire[31:0] instruction_decode_bus_valueB;
	wire[31:0] instruction_decode_bus_store_value;
	
	reg execution_bus_valid;
	reg[5:0] execution_bus_operation;
	reg[4:0] execution_bus_destination;
	reg[31:0] execution_bus_result;
	reg[31:0] execution_bus_store_value;
	//reg[31:0] tmp;
	
	assign instruction_decode_bus_valid = instruction_decode_bus[107];
	assign instruction_decode_bus_operation = instruction_decode_bus[106:101];
	assign instruction_decode_bus_destination = instruction_decode_bus[100:96];
	assign instruction_decode_bus_valueA = instruction_decode_bus[95:64];
	assign instruction_decode_bus_valueB = instruction_decode_bus[63:32];
	assign instruction_decode_bus_store_value = instruction_decode_bus[31:0];
	
	always @(posedge clk)
		begin
			if(reset || ! instruction_decode_bus_valid)
				begin
					execution_bus_valid <= 0;
					execution_bus_destination <= 5'b00000;
				end
			else
				begin
					execution_bus_operation <= instruction_decode_bus_operation;
					execution_bus_valid <= instruction_decode_bus_valid;
					execution_bus_destination <= instruction_decode_bus_destination;
					execution_bus_store_value <= instruction_decode_bus_store_value;
						
					case(execution_bus_operation)
						6'b100000:          //add
								execution_bus_result <= instruction_decode_bus_valueA + instruction_decode_bus_valueB;
						6'b100010:          //sub
								execution_bus_result <= instruction_decode_bus_valueA - instruction_decode_bus_valueB;
						6'b100100:          //and
								execution_bus_result <= instruction_decode_bus_valueA & instruction_decode_bus_valueB;
						6'b100101:          //or
								execution_bus_result <= instruction_decode_bus_valueA | instruction_decode_bus_valueB;
						6'b101010:          //slt
								execution_bus_result <= (instruction_decode_bus_valueA < instruction_decode_bus_valueB) ? 32'h00000001 : 32'h00000000;
						6'b001000:         //addi
								execution_bus_result <= instruction_decode_bus_valueA + instruction_decode_bus_valueB;
						6'b001100:         //andi
								execution_bus_result <= instruction_decode_bus_valueA & instruction_decode_bus_valueB;
						6'b001101:         //ori
								execution_bus_result <= instruction_decode_bus_valueA | instruction_decode_bus_valueB;
						6'b100011:         //lw
								execution_bus_result <= instruction_decode_bus_valueA + instruction_decode_bus_valueB;
						6'b101011:         //sw
								begin
									execution_bus_result <= instruction_decode_bus_valueA + instruction_decode_bus_valueB;
									execution_bus_destination <= 0;  //store instruction will not stall the pipeline							
								end
						6'b000100:         //bne
								begin
									//do nothing
								end
						6'b000101:         //beq
								begin
									//do nothing
								end
						6'b000010:         //j
								begin
									//do nothing
								end
					endcase
										
				end
		end
		
	assign execution_destination = execution_bus_destination;
	
	assign execution_bus[75] = execution_bus_valid;
	assign execution_bus[74:69] = execution_bus_operation;
	assign execution_bus[68:64] = execution_bus_destination;
	assign execution_bus[63:32] = execution_bus_result;
	assign execution_bus[31:0] = execution_bus_store_value;
endmodule