prev_cmp_clock.tan.qmsg

VHDL实现的电子钟的基本功能

{ "Info" "ITDB_FULL_TCO_RESULT" "clk hourh\[2\] counter24:u5\|count\[2\] 47.520 ns register " "Info: tco from clock \"clk\" to destination pin \"hourh\[2\]\" through register \"counter24:u5\|count\[2\]\" is 47.520 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 34.345 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 34.345 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.970 ns) 0.970 ns clk 1 CLK PIN_F2 5 " "Info: 1: + IC(0.000 ns) + CELL(0.970 ns) = 0.970 ns; Loc. = PIN_F2; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/quretus/eleclock/clock.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.590 ns) + CELL(2.113 ns) 4.673 ns counter10:u1\|c 2 REG LC_X8_Y4_N9 4 " "Info: 2: + IC(1.590 ns) + CELL(2.113 ns) = 4.673 ns; Loc. = LC_X8_Y4_N9; Fanout = 4; REG Node = 'counter10:u1\|c'" {  } { { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.703 ns" { clk counter10:u1|c } "NODE_NAME" } } { "counter10.vhd" "" { Text "E:/quretus/eleclock/counter10.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.641 ns) + CELL(2.113 ns) 13.427 ns counter6:u2\|c 3 REG LC_X11_Y4_N9 5 " "Info: 3: + IC(6.641 ns) + CELL(2.113 ns) = 13.427 ns; Loc. = LC_X11_Y4_N9; Fanout = 5; REG Node = 'counter6:u2\|c'" {  } { { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "8.754 ns" { counter10:u1|c counter6:u2|c } "NODE_NAME" } } { "counter6.vhd" "" { Text "E:/quretus/eleclock/counter6.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.010 ns) + CELL(2.113 ns) 21.550 ns counter10:u3\|c 4 REG LC_X10_Y6_N9 4 " "Info: 4: + IC(6.010 ns) + CELL(2.113 ns) = 21.550 ns; Loc. = LC_X10_Y6_N9; Fanout = 4; REG Node = 'counter10:u3\|c'" {  } { { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "8.123 ns" { counter6:u2|c counter10:u3|c } "NODE_NAME" } } { "counter10.vhd" "" { Text "E:/quretus/eleclock/counter10.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.286 ns) + CELL(2.113 ns) 27.949 ns counter6:u4\|c 5 REG LC_X9_Y4_N7 6 " "Info: 5: + IC(4.286 ns) + CELL(2.113 ns) = 27.949 ns; Loc. = LC_X9_Y4_N7; Fanout = 6; REG Node = 'counter6:u4\|c'" {  } { { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.399 ns" { counter10:u3|c counter6:u4|c } "NODE_NAME" } } { "counter6.vhd" "" { Text "E:/quretus/eleclock/counter6.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.772 ns) + CELL(1.624 ns) 34.345 ns counter24:u5\|count\[2\] 6 REG LC_X7_Y6_N6 12 " "Info: 6: + IC(4.772 ns) + CELL(1.624 ns) = 34.345 ns; Loc. = LC_X7_Y6_N6; Fanout = 12; REG Node = 'counter24:u5\|count\[2\]'" {  } { { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.396 ns" { counter6:u4|c counter24:u5|count[2] } "NODE_NAME" } } { "counter24.vhd" "" { Text "E:/quretus/eleclock/counter24.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.046 ns ( 32.16 % ) " "Info: Total cell delay = 11.046 ns ( 32.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "23.299 ns ( 67.84 % ) " "Info: Total interconnect delay = 23.299 ns ( 67.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "34.345 ns" { clk counter10:u1|c counter6:u2|c counter10:u3|c counter6:u4|c counter24:u5|count[2] } "NODE_NAME" } } { "d:/program files/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/quartus/bin/Technology_Viewer.qrui" "34.345 ns" { clk {} clk~combout {} counter10:u1|c {} counter6:u2|c {} counter10:u3|c {} counter6:u4|c {} counter24:u5|count[2] {} } { 0.000ns 0.000ns 1.590ns 6.641ns 6.010ns 4.286ns 4.772ns } { 0.000ns 0.970ns 2.113ns 2.113ns 2.113ns 2.113ns 1.624ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.489 ns + " "Info: + Micro clock to output delay of source is 0.489 ns" {  } { { "counter24.vhd" "" { Text "E:/quretus/eleclock/counter24.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.686 ns + Longest register pin " "Info: + Longest register to pin delay is 12.686 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter24:u5\|count\[2\] 1 REG LC_X7_Y6_N6 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y6_N6; Fanout = 12; REG Node = 'counter24:u5\|count\[2\]'" {  } { { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter24:u5|count[2] } "NODE_NAME" } } { "counter24.vhd" "" { Text "E:/quretus/eleclock/counter24.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.169 ns) + CELL(0.968 ns) 4.137 ns decoder:u10\|Mux4~29 2 COMB LC_X8_Y6_N1 1 " "Info: 2: + IC(3.169 ns) + CELL(0.968 ns) = 4.137 ns; Loc. = LC_X8_Y6_N1; Fanout = 1; COMB Node = 'decoder:u10\|Mux4~29'" {  } { { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.137 ns" { counter24:u5|count[2] decoder:u10|Mux4~29 } "NODE_NAME" } } { "decoder.vhd" "" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.575 ns) + CELL(1.974 ns) 12.686 ns hourh\[2\] 3 PIN PIN_D1 0 " "Info: 3: + IC(6.575 ns) + CELL(1.974 ns) = 12.686 ns; Loc. = PIN_D1; Fanout = 0; PIN Node = 'hourh\[2\]'" {  } { { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "8.549 ns" { decoder:u10|Mux4~29 hourh[2] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/quretus/eleclock/clock.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.942 ns ( 23.19 % ) " "Info: Total cell delay = 2.942 ns ( 23.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.744 ns ( 76.81 % ) " "Info: Total interconnect delay = 9.744 ns ( 76.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "12.686 ns" { counter24:u5|count[2] decoder:u10|Mux4~29 hourh[2] } "NODE_NAME" } } { "d:/program files/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/quartus/bin/Technology_Viewer.qrui" "12.686 ns" { counter24:u5|count[2] {} decoder:u10|Mux4~29 {} hourh[2] {} } { 0.000ns 3.169ns 6.575ns } { 0.000ns 0.968ns 1.974ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "34.345 ns" { clk counter10:u1|c counter6:u2|c counter10:u3|c counter6:u4|c counter24:u5|count[2] } "NODE_NAME" } } { "d:/program files/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/quartus/bin/Technology_Viewer.qrui" "34.345 ns" { clk {} clk~combout {} counter10:u1|c {} counter6:u2|c {} counter10:u3|c {} counter6:u4|c {} counter24:u5|count[2] {} } { 0.000ns 0.000ns 1.590ns 6.641ns 6.010ns 4.286ns 4.772ns } { 0.000ns 0.970ns 2.113ns 2.113ns 2.113ns 2.113ns 1.624ns } "" } } { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "12.686 ns" { counter24:u5|count[2] decoder:u10|Mux4~29 hourh[2] } "NODE_NAME" } } { "d:/program files/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/quartus/bin/Technology_Viewer.qrui" "12.686 ns" { counter24:u5|count[2] {} decoder:u10|Mux4~29 {} hourh[2] {} } { 0.000ns 3.169ns 6.575ns } { 0.000ns 0.968ns 1.974ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "IQCU_PARALLEL_UNUSED" "" "Info: Parallel compilation was enabled but no parallel operations were performed" {  } {  } 0 0 "Parallel compilation was enabled but no parallel operations were performed" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "124 " "Info: Peak virtual memory: 124 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 17 10:28:10 2009 " "Info: Processing ended: Fri Apr 17 10:28:10 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}