prev_cmp_clock.tan.qmsg

VHDL实现的电子钟的基本功能

{ "Warning" "WDAT_PRELIMINARY_TIMING" "EPM570ZM100C7 " "Warning: Timing characteristics of device EPM570ZM100C7 are preliminary" {  } {  } 0 0 "Timing characteristics of device %1!s! are preliminary" 0 0 "" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "clock.vhd" "" { Text "E:/quretus/eleclock/clock.vhd" 9 -1 0 } } { "d:/program files/quartus/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "counter6:u4\|c " "Info: Detected ripple clock \"counter6:u4\|c\" as buffer" {  } { { "counter6.vhd" "" { Text "E:/quretus/eleclock/counter6.vhd" 13 -1 0 } } { "d:/program files/quartus/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus/quartus/bin/Assignment Editor.qase" 1 { { 0 "counter6:u4\|c" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "counter10:u3\|c " "Info: Detected ripple clock \"counter10:u3\|c\" as buffer" {  } { { "counter10.vhd" "" { Text "E:/quretus/eleclock/counter10.vhd" 13 -1 0 } } { "d:/program files/quartus/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus/quartus/bin/Assignment Editor.qase" 1 { { 0 "counter10:u3\|c" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "counter6:u2\|c " "Info: Detected ripple clock \"counter6:u2\|c\" as buffer" {  } { { "counter6.vhd" "" { Text "E:/quretus/eleclock/counter6.vhd" 13 -1 0 } } { "d:/program files/quartus/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus/quartus/bin/Assignment Editor.qase" 1 { { 0 "counter6:u2\|c" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "counter10:u1\|c " "Info: Detected ripple clock \"counter10:u1\|c\" as buffer" {  } { { "counter10.vhd" "" { Text "E:/quretus/eleclock/counter10.vhd" 13 -1 0 } } { "d:/program files/quartus/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus/quartus/bin/Assignment Editor.qase" 1 { { 0 "counter10:u1\|c" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register counter24:u5\|count\[0\] register counter24:u5\|count\[5\] 78.97 MHz 12.663 ns Internal " "Info: Clock \"clk\" has Internal fmax of 78.97 MHz between source register \"counter24:u5\|count\[0\]\" and destination register \"counter24:u5\|count\[5\]\" (period= 12.663 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.855 ns + Longest register register " "Info: + Longest register to register delay is 11.855 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter24:u5\|count\[0\] 1 REG LC_X8_Y6_N0 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y6_N0; Fanout = 13; REG Node = 'counter24:u5\|count\[0\]'" {  } { { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter24:u5|count[0] } "NODE_NAME" } } { "counter24.vhd" "" { Text "E:/quretus/eleclock/counter24.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.206 ns) + CELL(2.247 ns) 6.453 ns counter24:u5\|Equal1~36 2 COMB LC_X8_Y6_N6 2 " "Info: 2: + IC(4.206 ns) + CELL(2.247 ns) = 6.453 ns; Loc. = LC_X8_Y6_N6; Fanout = 2; COMB Node = 'counter24:u5\|Equal1~36'" {  } { { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.453 ns" { counter24:u5|count[0] counter24:u5|Equal1~36 } "NODE_NAME" } } { "d:/program files/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.477 ns) + CELL(2.925 ns) 11.855 ns counter24:u5\|count\[5\] 3 REG LC_X7_Y6_N3 6 " "Info: 3: + IC(2.477 ns) + CELL(2.925 ns) = 11.855 ns; Loc. = LC_X7_Y6_N3; Fanout = 6; REG Node = 'counter24:u5\|count\[5\]'" {  } { { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.402 ns" { counter24:u5|Equal1~36 counter24:u5|count[5] } "NODE_NAME" } } { "counter24.vhd" "" { Text "E:/quretus/eleclock/counter24.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.172 ns ( 43.63 % ) " "Info: Total cell delay = 5.172 ns ( 43.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.683 ns ( 56.37 % ) " "Info: Total interconnect delay = 6.683 ns ( 56.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "11.855 ns" { counter24:u5|count[0] counter24:u5|Equal1~36 counter24:u5|count[5] } "NODE_NAME" } } { "d:/program files/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/quartus/bin/Technology_Viewer.qrui" "11.855 ns" { counter24:u5|count[0] {} counter24:u5|Equal1~36 {} counter24:u5|count[5] {} } { 0.000ns 4.206ns 2.477ns } { 0.000ns 2.247ns 2.925ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 34.345 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 34.345 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.970 ns) 0.970 ns clk 1 CLK PIN_F2 5 " "Info: 1: + IC(0.000 ns) + CELL(0.970 ns) = 0.970 ns; Loc. = PIN_F2; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/quretus/eleclock/clock.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.590 ns) + CELL(2.113 ns) 4.673 ns counter10:u1\|c 2 REG LC_X8_Y4_N9 4 " "Info: 2: + IC(1.590 ns) + CELL(2.113 ns) = 4.673 ns; Loc. = LC_X8_Y4_N9; Fanout = 4; REG Node = 'counter10:u1\|c'" {  } { { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.703 ns" { clk counter10:u1|c } "NODE_NAME" } } { "counter10.vhd" "" { Text "E:/quretus/eleclock/counter10.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.641 ns) + CELL(2.113 ns) 13.427 ns counter6:u2\|c 3 REG LC_X11_Y4_N9 5 " "Info: 3: + IC(6.641 ns) + CELL(2.113 ns) = 13.427 ns; Loc. = LC_X11_Y4_N9; Fanout = 5; REG Node = 'counter6:u2\|c'" {  } { { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "8.754 ns" { counter10:u1|c counter6:u2|c } "NODE_NAME" } } { "counter6.vhd" "" { Text "E:/quretus/eleclock/counter6.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.010 ns) + CELL(2.113 ns) 21.550 ns counter10:u3\|c 4 REG LC_X10_Y6_N9 4 " "Info: 4: + IC(6.010 ns) + CELL(2.113 ns) = 21.550 ns; Loc. = LC_X10_Y6_N9; Fanout = 4; REG Node = 'counter10:u3\|c'" {  } { { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "8.123 ns" { counter6:u2|c counter10:u3|c } "NODE_NAME" } } { "counter10.vhd" "" { Text "E:/quretus/eleclock/counter10.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.286 ns) + CELL(2.113 ns) 27.949 ns counter6:u4\|c 5 REG LC_X9_Y4_N7 6 " "Info: 5: + IC(4.286 ns) + CELL(2.113 ns) = 27.949 ns; Loc. = LC_X9_Y4_N7; Fanout = 6; REG Node = 'counter6:u4\|c'" {  } { { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.399 ns" { counter10:u3|c counter6:u4|c } "NODE_NAME" } } { "counter6.vhd" "" { Text "E:/quretus/eleclock/counter6.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.772 ns) + CELL(1.624 ns) 34.345 ns counter24:u5\|count\[5\] 6 REG LC_X7_Y6_N3 6 " "Info: 6: + IC(4.772 ns) + CELL(1.624 ns) = 34.345 ns; Loc. = LC_X7_Y6_N3; Fanout = 6; REG Node = 'counter24:u5\|count\[5\]'" {  } { { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.396 ns" { counter6:u4|c counter24:u5|count[5] } "NODE_NAME" } } { "counter24.vhd" "" { Text "E:/quretus/eleclock/counter24.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.046 ns ( 32.16 % ) " "Info: Total cell delay = 11.046 ns ( 32.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "23.299 ns ( 67.84 % ) " "Info: Total interconnect delay = 23.299 ns ( 67.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "34.345 ns" { clk counter10:u1|c counter6:u2|c counter10:u3|c counter6:u4|c counter24:u5|count[5] } "NODE_NAME" } } { "d:/program files/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/quartus/bin/Technology_Viewer.qrui" "34.345 ns" { clk {} clk~combout {} counter10:u1|c {} counter6:u2|c {} counter10:u3|c {} counter6:u4|c {} counter24:u5|count[5] {} } { 0.000ns 0.000ns 1.590ns 6.641ns 6.010ns 4.286ns 4.772ns } { 0.000ns 0.970ns 2.113ns 2.113ns 2.113ns 2.113ns 1.624ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 34.345 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 34.345 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.970 ns) 0.970 ns clk 1 CLK PIN_F2 5 " "Info: 1: + IC(0.000 ns) + CELL(0.970 ns) = 0.970 ns; Loc. = PIN_F2; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/quretus/eleclock/clock.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.590 ns) + CELL(2.113 ns) 4.673 ns counter10:u1\|c 2 REG LC_X8_Y4_N9 4 " "Info: 2: + IC(1.590 ns) + CELL(2.113 ns) = 4.673 ns; Loc. = LC_X8_Y4_N9; Fanout = 4; REG Node = 'counter10:u1\|c'" {  } { { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.703 ns" { clk counter10:u1|c } "NODE_NAME" } } { "counter10.vhd" "" { Text "E:/quretus/eleclock/counter10.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.641 ns) + CELL(2.113 ns) 13.427 ns counter6:u2\|c 3 REG LC_X11_Y4_N9 5 " "Info: 3: + IC(6.641 ns) + CELL(2.113 ns) = 13.427 ns; Loc. = LC_X11_Y4_N9; Fanout = 5; REG Node = 'counter6:u2\|c'" {  } { { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "8.754 ns" { counter10:u1|c counter6:u2|c } "NODE_NAME" } } { "counter6.vhd" "" { Text "E:/quretus/eleclock/counter6.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.010 ns) + CELL(2.113 ns) 21.550 ns counter10:u3\|c 4 REG LC_X10_Y6_N9 4 " "Info: 4: + IC(6.010 ns) + CELL(2.113 ns) = 21.550 ns; Loc. = LC_X10_Y6_N9; Fanout = 4; REG Node = 'counter10:u3\|c'" {  } { { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "8.123 ns" { counter6:u2|c counter10:u3|c } "NODE_NAME" } } { "counter10.vhd" "" { Text "E:/quretus/eleclock/counter10.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.286 ns) + CELL(2.113 ns) 27.949 ns counter6:u4\|c 5 REG LC_X9_Y4_N7 6 " "Info: 5: + IC(4.286 ns) + CELL(2.113 ns) = 27.949 ns; Loc. = LC_X9_Y4_N7; Fanout = 6; REG Node = 'counter6:u4\|c'" {  } { { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.399 ns" { counter10:u3|c counter6:u4|c } "NODE_NAME" } } { "counter6.vhd" "" { Text "E:/quretus/eleclock/counter6.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.772 ns) + CELL(1.624 ns) 34.345 ns counter24:u5\|count\[0\] 6 REG LC_X8_Y6_N0 13 " "Info: 6: + IC(4.772 ns) + CELL(1.624 ns) = 34.345 ns; Loc. = LC_X8_Y6_N0; Fanout = 13; REG Node = 'counter24:u5\|count\[0\]'" {  } { { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.396 ns" { counter6:u4|c counter24:u5|count[0] } "NODE_NAME" } } { "counter24.vhd" "" { Text "E:/quretus/eleclock/counter24.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.046 ns ( 32.16 % ) " "Info: Total cell delay = 11.046 ns ( 32.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "23.299 ns ( 67.84 % ) " "Info: Total interconnect delay = 23.299 ns ( 67.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "34.345 ns" { clk counter10:u1|c counter6:u2|c counter10:u3|c counter6:u4|c counter24:u5|count[0] } "NODE_NAME" } } { "d:/program files/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/quartus/bin/Technology_Viewer.qrui" "34.345 ns" { clk {} clk~combout {} counter10:u1|c {} counter6:u2|c {} counter10:u3|c {} counter6:u4|c {} counter24:u5|count[0] {} } { 0.000ns 0.000ns 1.590ns 6.641ns 6.010ns 4.286ns 4.772ns } { 0.000ns 0.970ns 2.113ns 2.113ns 2.113ns 2.113ns 1.624ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "34.345 ns" { clk counter10:u1|c counter6:u2|c counter10:u3|c counter6:u4|c counter24:u5|count[5] } "NODE_NAME" } } { "d:/program files/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/quartus/bin/Technology_Viewer.qrui" "34.345 ns" { clk {} clk~combout {} counter10:u1|c {} counter6:u2|c {} counter10:u3|c {} counter6:u4|c {} counter24:u5|count[5] {} } { 0.000ns 0.000ns 1.590ns 6.641ns 6.010ns 4.286ns 4.772ns } { 0.000ns 0.970ns 2.113ns 2.113ns 2.113ns 2.113ns 1.624ns } "" } } { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "34.345 ns" { clk counter10:u1|c counter6:u2|c counter10:u3|c counter6:u4|c counter24:u5|count[0] } "NODE_NAME" } } { "d:/program files/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/quartus/bin/Technology_Viewer.qrui" "34.345 ns" { clk {} clk~combout {} counter10:u1|c {} counter6:u2|c {} counter10:u3|c {} counter6:u4|c {} counter24:u5|count[0] {} } { 0.000ns 0.000ns 1.590ns 6.641ns 6.010ns 4.286ns 4.772ns } { 0.000ns 0.970ns 2.113ns 2.113ns 2.113ns 2.113ns 1.624ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.489 ns + " "Info: + Micro clock to output delay of source is 0.489 ns" {  } { { "counter24.vhd" "" { Text "E:/quretus/eleclock/counter24.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.319 ns + " "Info: + Micro setup delay of destination is 0.319 ns" {  } { { "counter24.vhd" "" { Text "E:/quretus/eleclock/counter24.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "11.855 ns" { counter24:u5|count[0] counter24:u5|Equal1~36 counter24:u5|count[5] } "NODE_NAME" } } { "d:/program files/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/quartus/bin/Technology_Viewer.qrui" "11.855 ns" { counter24:u5|count[0] {} counter24:u5|Equal1~36 {} counter24:u5|count[5] {} } { 0.000ns 4.206ns 2.477ns } { 0.000ns 2.247ns 2.925ns } "" } } { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "34.345 ns" { clk counter10:u1|c counter6:u2|c counter10:u3|c counter6:u4|c counter24:u5|count[5] } "NODE_NAME" } } { "d:/program files/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/quartus/bin/Technology_Viewer.qrui" "34.345 ns" { clk {} clk~combout {} counter10:u1|c {} counter6:u2|c {} counter10:u3|c {} counter6:u4|c {} counter24:u5|count[5] {} } { 0.000ns 0.000ns 1.590ns 6.641ns 6.010ns 4.286ns 4.772ns } { 0.000ns 0.970ns 2.113ns 2.113ns 2.113ns 2.113ns 1.624ns } "" } } { "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "34.345 ns" { clk counter10:u1|c counter6:u2|c counter10:u3|c counter6:u4|c counter24:u5|count[0] } "NODE_NAME" } } { "d:/program files/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/quartus/bin/Technology_Viewer.qrui" "34.345 ns" { clk {} clk~combout {} counter10:u1|c {} counter6:u2|c {} counter10:u3|c {} counter6:u4|c {} counter24:u5|count[0] {} } { 0.000ns 0.000ns 1.590ns 6.641ns 6.010ns 4.286ns 4.772ns } { 0.000ns 0.970ns 2.113ns 2.113ns 2.113ns 2.113ns 1.624ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}