exp9.tan.qmsg

来自「四人抢答器」· QMSG 代码 · 共 11 行 · 第 1/4 页

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Clk " "Info: Assuming node \"Clk\" is an undefined clock" {  } { { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 13 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "Clk register memory SEG_SEL\[0\]~reg0 altsyncram:Disp_Decode_rtl_0\|altsyncram_77l:auto_generated\|ram_block1a0~porta_address_reg1 180.05 MHz Internal " "Info: Clock \"Clk\" Internal fmax is restricted to 180.05 MHz between source register \"SEG_SEL\[0\]~reg0\" and destination memory \"altsyncram:Disp_Decode_rtl_0\|altsyncram_77l:auto_generated\|ram_block1a0~porta_address_reg1\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.777 ns 2.777 ns 5.554 ns " "Info: fmax restricted to Clock High delay (2.777 ns) plus Clock Low delay (2.777 ns) : restricted to 5.554 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.040 ns + Longest register memory " "Info: + Longest register to memory delay is 5.040 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SEG_SEL\[0\]~reg0 1 REG LCFF_X27_Y1_N19 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X27_Y1_N19; Fanout = 10; REG Node = 'SEG_SEL\[0\]~reg0'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "" { SEG_SEL[0]~reg0 } "NODE_NAME" } "" } } { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 79 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.651 ns) 1.433 ns Disp_Temp\[1\]~1343 2 COMB LCCOMB_X27_Y1_N14 1 " "Info: 2: + IC(0.782 ns) + CELL(0.651 ns) = 1.433 ns; Loc. = LCCOMB_X27_Y1_N14; Fanout = 1; COMB Node = 'Disp_Temp\[1\]~1343'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "1.433 ns" { SEG_SEL[0]~reg0 Disp_Temp[1]~1343 } "NODE_NAME" } "" } } { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.599 ns) + CELL(0.651 ns) 2.683 ns Disp_Temp\[1\]~1345 3 COMB LCCOMB_X27_Y1_N0 1 " "Info: 3: + IC(0.599 ns) + CELL(0.651 ns) = 2.683 ns; Loc. = LCCOMB_X27_Y1_N0; Fanout = 1; COMB Node = 'Disp_Temp\[1\]~1345'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "1.250 ns" { Disp_Temp[1]~1343 Disp_Temp[1]~1345 } "NODE_NAME" } "" } } { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.048 ns) + CELL(0.319 ns) 4.050 ns Disp_Temp\[1\]~1347 4 COMB LCCOMB_X27_Y1_N16 1 " "Info: 4: + IC(1.048 ns) + CELL(0.319 ns) = 4.050 ns; Loc. = LCCOMB_X27_Y1_N16; Fanout = 1; COMB Node = 'Disp_Temp\[1\]~1347'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "1.367 ns" { Disp_Temp[1]~1345 Disp_Temp[1]~1347 } "NODE_NAME" } "" } } { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.814 ns) + CELL(0.176 ns) 5.040 ns altsyncram:Disp_Decode_rtl_0\|altsyncram_77l:auto_generated\|ram_block1a0~porta_address_reg1 5 MEM M4K_X26_Y1 7 " "Info: 5: + IC(0.814 ns) + CELL(0.176 ns) = 5.040 ns; Loc. = M4K_X26_Y1; Fanout = 7; MEM Node = 'altsyncram:Disp_Decode_rtl_0\|altsyncram_77l:auto_generated\|ram_block1a0~porta_address_reg1'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "0.990 ns" { Disp_Temp[1]~1347 altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } "" } } { "db/altsyncram_77l.tdf" "" { Text "D:/work/add/db/altsyncram_77l.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.797 ns ( 35.65 % ) " "Info: Total cell delay = 1.797 ns ( 35.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.243 ns ( 64.35 % ) " "Info: Total interconnect delay = 3.243 ns ( 64.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "5.040 ns" { SEG_SEL[0]~reg0 Disp_Temp[1]~1343 Disp_Temp[1]~1345 Disp_Temp[1]~1347 altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "5.040 ns" { SEG_SEL[0]~reg0 Disp_Temp[1]~1343 Disp_Temp[1]~1345 Disp_Temp[1]~1347 altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1 } { 0.000ns 0.782ns 0.599ns 1.048ns 0.814ns } { 0.000ns 0.651ns 0.651ns 0.319ns 0.176ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.097 ns - Smallest " "Info: - Smallest clock skew is 0.097 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 3.225 ns + Shortest memory " "Info: + Shortest clock path from clock \"Clk\" to destination memory is 3.225 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns Clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'Clk'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "" { Clk } "NODE_NAME" } "" } } { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.239 ns Clk~clkctrl 2 COMB CLKCTRL_G2 7 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'Clk~clkctrl'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "0.139 ns" { Clk Clk~clkctrl } "NODE_NAME" } "" } } { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.151 ns) + CELL(0.835 ns) 3.225 ns altsyncram:Disp_Decode_rtl_0\|altsyncram_77l:auto_generated\|ram_block1a0~porta_address_reg1 3 MEM M4K_X26_Y1 7 " "Info: 3: + IC(1.151 ns) + CELL(0.835 ns) = 3.225 ns; Loc. = M4K_X26_Y1; Fanout = 7; MEM Node = 'altsyncram:Disp_Decode_rtl_0\|altsyncram_77l:auto_generated\|ram_block1a0~porta_address_reg1'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "1.986 ns" { Clk~clkctrl altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } "" } } { "db/altsyncram_77l.tdf" "" { Text "D:/work/add/db/altsyncram_77l.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.935 ns ( 60.00 % ) " "Info: Total cell delay = 1.935 ns ( 60.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.290 ns ( 40.00 % ) " "Info: Total interconnect delay = 1.290 ns ( 40.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "3.225 ns" { Clk Clk~clkctrl altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "3.225 ns" { Clk Clk~combout Clk~clkctrl altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1 } { 0.000ns 0.000ns 0.139ns 1.151ns } { 0.000ns 1.100ns 0.000ns 0.835ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 3.128 ns - Longest register " "Info: - Longest clock path from clock \"Clk\" to source register is 3.128 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns Clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'Clk'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "" { Clk } "NODE_NAME" } "" } } { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.239 ns Clk~clkctrl 2 COMB CLKCTRL_G2 7 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'Clk~clkctrl'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "0.139 ns" { Clk Clk~clkctrl } "NODE_NAME" } "" } } { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.223 ns) + CELL(0.666 ns) 3.128 ns SEG_SEL\[0\]~reg0 3 REG LCFF_X27_Y1_N19 10 " "Info: 3: + IC(1.223 ns) + CELL(0.666 ns) = 3.128 ns; Loc. = LCFF_X27_Y1_N19; Fanout = 10; REG Node = 'SEG_SEL\[0\]~reg0'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "1.889 ns" { Clk~clkctrl SEG_SEL[0]~reg0 } "NODE_NAME" } "" } } { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 79 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 56.46 % ) " "Info: Total cell delay = 1.766 ns ( 56.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.362 ns ( 43.54 % ) " "Info: Total interconnect delay = 1.362 ns ( 43.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "3.128 ns" { Clk Clk~clkctrl SEG_SEL[0]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "3.128 ns" { Clk Clk~combout Clk~clkctrl SEG_SEL[0]~reg0 } { 0.000ns 0.000ns 0.139ns 1.223ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "3.225 ns" { Clk Clk~clkctrl altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "3.225 ns" { Clk Clk~combout Clk~clkctrl altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1 } { 0.000ns 0.000ns 0.139ns 1.151ns } { 0.000ns 1.100ns 0.000ns 0.835ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "3.128 ns" { Clk Clk~clkctrl SEG_SEL[0]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "3.128 ns" { Clk Clk~combout Clk~clkctrl SEG_SEL[0]~reg0 } { 0.000ns 0.000ns 0.139ns 1.223ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 79 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.046 ns + " "Info: + Micro setup delay of destination is 0.046 ns" {  } { { "db/altsyncram_77l.tdf" "" { Text "D:/work/add/db/altsyncram_77l.tdf" 43 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "5.040 ns" { SEG_SEL[0]~reg0 Disp_Temp[1]~1343 Disp_Temp[1]~1345 Disp_Temp[1]~1347 altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "5.040 ns" { SEG_SEL[0]~reg0 Disp_Temp[1]~1343 Disp_Temp[1]~1345 Disp_Temp[1]~1347 altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1 } { 0.000ns 0.782ns 0.599ns 1.048ns 0.814ns } { 0.000ns 0.651ns 0.651ns 0.319ns 0.176ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "3.225 ns" { Clk Clk~clkctrl altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "3.225 ns" { Clk Clk~combout Clk~clkctrl altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1 } { 0.000ns 0.000ns 0.139ns 1.151ns } { 0.000ns 1.100ns 0.000ns 0.835ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "3.128 ns" { Clk Clk~clkctrl SEG_SEL[0]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "3.128 ns" { Clk Clk~combout Clk~clkctrl SEG_SEL[0]~reg0 } { 0.000ns 0.000ns 0.139ns 1.223ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "" { altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1 } {  } {  } } } { "db/altsyncram_77l.tdf" "" { Text "D:/work/add/db/altsyncram_77l.tdf" 43 2 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "altsyncram:Disp_Decode_rtl_0\|altsyncram_77l:auto_generated\|ram_block1a0~porta_address_reg1 Y\[1\] Clk 12.825 ns memory " "Info: tsu for memory \"altsyncram:Disp_Decode_rtl_0\|altsyncram_77l:auto_generated\|ram_block1a0~porta_address_reg1\" (data pin = \"Y\[1\]\", clock pin = \"Clk\") is 12.825 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.004 ns + Longest pin memory " "Info: + Longest pin to memory delay is 16.004 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.904 ns) 0.904 ns Y\[1\] 1 PIN PIN_AA10 2 " "Info: 1: + IC(0.000 ns) + CELL(0.904 ns) = 0.904 ns; Loc. = PIN_AA10; Fanout = 2; PIN Node = 'Y\[1\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "" { Y[1] } "NODE_NAME" } "" } } { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.977 ns) + CELL(0.651 ns) 8.532 ns S2~18 2 COMB LCCOMB_X25_Y1_N12 5 " "Info: 2: + IC(6.977 ns) + CELL(0.651 ns) = 8.532 ns; Loc. = LCCOMB_X25_Y1_N12; Fanout = 5; COMB Node = 'S2~18'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "7.628 ns" { Y[1] S2~18 } "NODE_NAME" } "" } } { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.404 ns) + CELL(0.206 ns) 9.142 ns S3~68 3 COMB LCCOMB_X25_Y1_N0 2 " "Info: 3: + IC(0.404 ns) + CELL(0.206 ns) = 9.142 ns; Loc. = LCCOMB_X25_Y1_N0; Fanout = 2; COMB Node = 'S3~68'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "0.610 ns" { S2~18 S3~68 } "NODE_NAME" } "" } } { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.367 ns) + CELL(0.624 ns) 10.133 ns result~3 4 COMB LCCOMB_X25_Y1_N2 8 " "Info: 4: + IC(0.367 ns) + CELL(0.624 ns) = 10.133 ns; Loc. = LCCOMB_X25_Y1_N2; Fanout = 8; COMB Node = 'result~3'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "0.991 ns" { S3~68 result~3 } "NODE_NAME" } "" } } { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.381 ns) + CELL(0.206 ns) 10.720 ns Disp_Temp\[3\]~1353 5 COMB LCCOMB_X25_Y1_N20 2 " "Info: 5: + IC(0.381 ns) + CELL(0.206 ns) = 10.720 ns; Loc. = LCCOMB_X25_Y1_N20; Fanout = 2; COMB Node = 'Disp_Temp\[3\]~1353'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "0.587 ns" { result~3 Disp_Temp[3]~1353 } "NODE_NAME" } "" } } { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.053 ns) + CELL(0.624 ns) 12.397 ns Disp_Temp\[1\]~1343 6 COMB LCCOMB_X27_Y1_N14 1 " "Info: 6: + IC(1.053 ns) + CELL(0.624 ns) = 12.397 ns; Loc. = LCCOMB_X27_Y1_N14; Fanout = 1; COMB Node = 'Disp_Temp\[1\]~1343'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "1.677 ns" { Disp_Temp[3]~1353 Disp_Temp[1]~1343 } "NODE_NAME" } "" } } { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.599 ns) + CELL(0.651 ns) 13.647 ns Disp_Temp\[1\]~1345 7 COMB LCCOMB_X27_Y1_N0 1 " "Info: 7: + IC(0.599 ns) + CELL(0.651 ns) = 13.647 ns; Loc. = LCCOMB_X27_Y1_N0; Fanout = 1; COMB Node = 'Disp_Temp\[1\]~1345'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "1.250 ns" { Disp_Temp[1]~1343 Disp_Temp[1]~1345 } "NODE_NAME" } "" } } { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.048 ns) + CELL(0.319 ns) 15.014 ns Disp_Temp\[1\]~1347 8 COMB LCCOMB_X27_Y1_N16 1 " "Info: 8: + IC(1.048 ns) + CELL(0.319 ns) = 15.014 ns; Loc. = LCCOMB_X27_Y1_N16; Fanout = 1; COMB Node = 'Disp_Temp\[1\]~1347'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "1.367 ns" { Disp_Temp[1]~1345 Disp_Temp[1]~1347 } "NODE_NAME" } "" } } { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.814 ns) + CELL(0.176 ns) 16.004 ns altsyncram:Disp_Decode_rtl_0\|altsyncram_77l:auto_generated\|ram_block1a0~porta_address_reg1 9 MEM M4K_X26_Y1 7 " "Info: 9: + IC(0.814 ns) + CELL(0.176 ns) = 16.004 ns; Loc. = M4K_X26_Y1; Fanout = 7; MEM Node = 'altsyncram:Disp_Decode_rtl_0\|altsyncram_77l:auto_generated\|ram_block1a0~porta_address_reg1'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "0.990 ns" { Disp_Temp[1]~1347 altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } "" } } { "db/altsyncram_77l.tdf" "" { Text "D:/work/add/db/altsyncram_77l.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.361 ns ( 27.25 % ) " "Info: Total cell delay = 4.361 ns ( 27.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.643 ns ( 72.75 % ) " "Info: Total interconnect delay = 11.643 ns ( 72.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "16.004 ns" { Y[1] S2~18 S3~68 result~3 Disp_Temp[3]~1353 Disp_Temp[1]~1343 Disp_Temp[1]~1345 Disp_Temp[1]~1347 altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "16.004 ns" { Y[1] Y[1]~combout S2~18 S3~68 result~3 Disp_Temp[3]~1353 Disp_Temp[1]~1343 Disp_Temp[1]~1345 Disp_Temp[1]~1347 altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1 } { 0.000ns 0.000ns 6.977ns 0.404ns 0.367ns 0.381ns 1.053ns 0.599ns 1.048ns 0.814ns } { 0.000ns 0.904ns 0.651ns 0.206ns 0.624ns 0.206ns 0.624ns 0.651ns 0.319ns 0.176ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.046 ns + " "Info: + Micro setup delay of destination is 0.046 ns" {  } { { "db/altsyncram_77l.tdf" "" { Text "D:/work/add/db/altsyncram_77l.tdf" 43 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 3.225 ns - Shortest memory " "Info: - Shortest clock path from clock \"Clk\" to destination memory is 3.225 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns Clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'Clk'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "" { Clk } "NODE_NAME" } "" } } { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.239 ns Clk~clkctrl 2 COMB CLKCTRL_G2 7 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'Clk~clkctrl'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "0.139 ns" { Clk Clk~clkctrl } "NODE_NAME" } "" } } { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.151 ns) + CELL(0.835 ns) 3.225 ns altsyncram:Disp_Decode_rtl_0\|altsyncram_77l:auto_generated\|ram_block1a0~porta_address_reg1 3 MEM M4K_X26_Y1 7 " "Info: 3: + IC(1.151 ns) + CELL(0.835 ns) = 3.225 ns; Loc. = M4K_X26_Y1; Fanout = 7; MEM Node = 'altsyncram:Disp_Decode_rtl_0\|altsyncram_77l:auto_generated\|ram_block1a0~porta_address_reg1'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "1.986 ns" { Clk~clkctrl altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } "" } } { "db/altsyncram_77l.tdf" "" { Text "D:/work/add/db/altsyncram_77l.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.935 ns ( 60.00 % ) " "Info: Total cell delay = 1.935 ns ( 60.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.290 ns ( 40.00 % ) " "Info: Total interconnect delay = 1.290 ns ( 40.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "3.225 ns" { Clk Clk~clkctrl altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "3.225 ns" { Clk Clk~combout Clk~clkctrl altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1 } { 0.000ns 0.000ns 0.139ns 1.151ns } { 0.000ns 1.100ns 0.000ns 0.835ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "16.004 ns" { Y[1] S2~18 S3~68 result~3 Disp_Temp[3]~1353 Disp_Temp[1]~1343 Disp_Temp[1]~1345 Disp_Temp[1]~1347 altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "16.004 ns" { Y[1] Y[1]~combout S2~18 S3~68 result~3 Disp_Temp[3]~1353 Disp_Temp[1]~1343 Disp_Temp[1]~1345 Disp_Temp[1]~1347 altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1 } { 0.000ns 0.000ns 6.977ns 0.404ns 0.367ns 0.381ns 1.053ns 0.599ns 1.048ns 0.814ns } { 0.000ns 0.904ns 0.651ns 0.206ns 0.624ns 0.206ns 0.624ns 0.651ns 0.319ns 0.176ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "3.225 ns" { Clk Clk~clkctrl altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "3.225 ns" { Clk Clk~combout Clk~clkctrl altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1 } { 0.000ns 0.000ns 0.139ns 1.151ns } { 0.000ns 1.100ns 0.000ns 0.835ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}