exp9.tan.qmsg

来自「四人抢答器」· QMSG 代码 · 共 11 行 · 第 1/4 页

{ "Info" "ITDB_FULL_TCO_RESULT" "Clk Display\[3\] altsyncram:Disp_Decode_rtl_0\|altsyncram_77l:auto_generated\|ram_block1a0~porta_address_reg0 15.681 ns memory " "Info: tco from clock \"Clk\" to destination pin \"Display\[3\]\" through memory \"altsyncram:Disp_Decode_rtl_0\|altsyncram_77l:auto_generated\|ram_block1a0~porta_address_reg0\" is 15.681 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 3.225 ns + Longest memory " "Info: + Longest clock path from clock \"Clk\" to source memory is 3.225 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns Clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'Clk'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "" { Clk } "NODE_NAME" } "" } } { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.239 ns Clk~clkctrl 2 COMB CLKCTRL_G2 7 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'Clk~clkctrl'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "0.139 ns" { Clk Clk~clkctrl } "NODE_NAME" } "" } } { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.151 ns) + CELL(0.835 ns) 3.225 ns altsyncram:Disp_Decode_rtl_0\|altsyncram_77l:auto_generated\|ram_block1a0~porta_address_reg0 3 MEM M4K_X26_Y1 7 " "Info: 3: + IC(1.151 ns) + CELL(0.835 ns) = 3.225 ns; Loc. = M4K_X26_Y1; Fanout = 7; MEM Node = 'altsyncram:Disp_Decode_rtl_0\|altsyncram_77l:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "1.986 ns" { Clk~clkctrl altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_77l.tdf" "" { Text "D:/work/add/db/altsyncram_77l.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.935 ns ( 60.00 % ) " "Info: Total cell delay = 1.935 ns ( 60.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.290 ns ( 40.00 % ) " "Info: Total interconnect delay = 1.290 ns ( 40.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "3.225 ns" { Clk Clk~clkctrl altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "3.225 ns" { Clk Clk~combout Clk~clkctrl altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.139ns 1.151ns } { 0.000ns 1.100ns 0.000ns 0.835ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.260 ns + " "Info: + Micro clock to output delay of source is 0.260 ns" {  } { { "db/altsyncram_77l.tdf" "" { Text "D:/work/add/db/altsyncram_77l.tdf" 43 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.196 ns + Longest memory pin " "Info: + Longest memory to pin delay is 12.196 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altsyncram:Disp_Decode_rtl_0\|altsyncram_77l:auto_generated\|ram_block1a0~porta_address_reg0 1 MEM M4K_X26_Y1 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X26_Y1; Fanout = 7; MEM Node = 'altsyncram:Disp_Decode_rtl_0\|altsyncram_77l:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "" { altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_77l.tdf" "" { Text "D:/work/add/db/altsyncram_77l.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.761 ns) 3.761 ns altsyncram:Disp_Decode_rtl_0\|altsyncram_77l:auto_generated\|q_a\[3\] 2 MEM M4K_X26_Y1 1 " "Info: 2: + IC(0.000 ns) + CELL(3.761 ns) = 3.761 ns; Loc. = M4K_X26_Y1; Fanout = 1; MEM Node = 'altsyncram:Disp_Decode_rtl_0\|altsyncram_77l:auto_generated\|q_a\[3\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "3.761 ns" { altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg0 altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|q_a[3] } "NODE_NAME" } "" } } { "db/altsyncram_77l.tdf" "" { Text "D:/work/add/db/altsyncram_77l.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.409 ns) + CELL(3.026 ns) 12.196 ns Display\[3\] 3 PIN PIN_L10 0 " "Info: 3: + IC(5.409 ns) + CELL(3.026 ns) = 12.196 ns; Loc. = PIN_L10; Fanout = 0; PIN Node = 'Display\[3\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "8.435 ns" { altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|q_a[3] Display[3] } "NODE_NAME" } "" } } { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 79 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.787 ns ( 55.65 % ) " "Info: Total cell delay = 6.787 ns ( 55.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.409 ns ( 44.35 % ) " "Info: Total interconnect delay = 5.409 ns ( 44.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "12.196 ns" { altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg0 altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|q_a[3] Display[3] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "12.196 ns" { altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg0 altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|q_a[3] Display[3] } { 0.000ns 0.000ns 5.409ns } { 0.000ns 3.761ns 3.026ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "3.225 ns" { Clk Clk~clkctrl altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "3.225 ns" { Clk Clk~combout Clk~clkctrl altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.139ns 1.151ns } { 0.000ns 1.100ns 0.000ns 0.835ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "12.196 ns" { altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg0 altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|q_a[3] Display[3] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "12.196 ns" { altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg0 altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|q_a[3] Display[3] } { 0.000ns 0.000ns 5.409ns } { 0.000ns 3.761ns 3.026ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "Y\[1\] result\[4\] 17.299 ns Longest " "Info: Longest tpd from source pin \"Y\[1\]\" to destination pin \"result\[4\]\" is 17.299 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.904 ns) 0.904 ns Y\[1\] 1 PIN PIN_AA10 2 " "Info: 1: + IC(0.000 ns) + CELL(0.904 ns) = 0.904 ns; Loc. = PIN_AA10; Fanout = 2; PIN Node = 'Y\[1\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "" { Y[1] } "NODE_NAME" } "" } } { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.977 ns) + CELL(0.651 ns) 8.532 ns S2~18 2 COMB LCCOMB_X25_Y1_N12 5 " "Info: 2: + IC(6.977 ns) + CELL(0.651 ns) = 8.532 ns; Loc. = LCCOMB_X25_Y1_N12; Fanout = 5; COMB Node = 'S2~18'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "7.628 ns" { Y[1] S2~18 } "NODE_NAME" } "" } } { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.404 ns) + CELL(0.206 ns) 9.142 ns S3~68 3 COMB LCCOMB_X25_Y1_N0 2 " "Info: 3: + IC(0.404 ns) + CELL(0.206 ns) = 9.142 ns; Loc. = LCCOMB_X25_Y1_N0; Fanout = 2; COMB Node = 'S3~68'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "0.610 ns" { S2~18 S3~68 } "NODE_NAME" } "" } } { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.373 ns) + CELL(0.624 ns) 10.139 ns result~223 4 COMB LCCOMB_X25_Y1_N22 8 " "Info: 4: + IC(0.373 ns) + CELL(0.624 ns) = 10.139 ns; Loc. = LCCOMB_X25_Y1_N22; Fanout = 8; COMB Node = 'result~223'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "0.997 ns" { S3~68 result~223 } "NODE_NAME" } "" } } { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.914 ns) + CELL(3.246 ns) 17.299 ns result\[4\] 5 PIN PIN_U18 0 " "Info: 5: + IC(3.914 ns) + CELL(3.246 ns) = 17.299 ns; Loc. = PIN_U18; Fanout = 0; PIN Node = 'result\[4\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "7.160 ns" { result~223 result[4] } "NODE_NAME" } "" } } { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.631 ns ( 32.55 % ) " "Info: Total cell delay = 5.631 ns ( 32.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.668 ns ( 67.45 % ) " "Info: Total interconnect delay = 11.668 ns ( 67.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "17.299 ns" { Y[1] S2~18 S3~68 result~223 result[4] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "17.299 ns" { Y[1] Y[1]~combout S2~18 S3~68 result~223 result[4] } { 0.000ns 0.000ns 6.977ns 0.404ns 0.373ns 3.914ns } { 0.000ns 0.904ns 0.651ns 0.206ns 0.624ns 3.246ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "altsyncram:Disp_Decode_rtl_0\|altsyncram_77l:auto_generated\|ram_block1a0~porta_address_reg3 Y\[3\] Clk -5.998 ns memory " "Info: th for memory \"altsyncram:Disp_Decode_rtl_0\|altsyncram_77l:auto_generated\|ram_block1a0~porta_address_reg3\" (data pin = \"Y\[3\]\", clock pin = \"Clk\") is -5.998 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 3.225 ns + Longest memory " "Info: + Longest clock path from clock \"Clk\" to destination memory is 3.225 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns Clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'Clk'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "" { Clk } "NODE_NAME" } "" } } { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.239 ns Clk~clkctrl 2 COMB CLKCTRL_G2 7 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'Clk~clkctrl'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "0.139 ns" { Clk Clk~clkctrl } "NODE_NAME" } "" } } { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.151 ns) + CELL(0.835 ns) 3.225 ns altsyncram:Disp_Decode_rtl_0\|altsyncram_77l:auto_generated\|ram_block1a0~porta_address_reg3 3 MEM M4K_X26_Y1 7 " "Info: 3: + IC(1.151 ns) + CELL(0.835 ns) = 3.225 ns; Loc. = M4K_X26_Y1; Fanout = 7; MEM Node = 'altsyncram:Disp_Decode_rtl_0\|altsyncram_77l:auto_generated\|ram_block1a0~porta_address_reg3'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "1.986 ns" { Clk~clkctrl altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg3 } "NODE_NAME" } "" } } { "db/altsyncram_77l.tdf" "" { Text "D:/work/add/db/altsyncram_77l.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.935 ns ( 60.00 % ) " "Info: Total cell delay = 1.935 ns ( 60.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.290 ns ( 40.00 % ) " "Info: Total interconnect delay = 1.290 ns ( 40.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "3.225 ns" { Clk Clk~clkctrl altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg3 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "3.225 ns" { Clk Clk~combout Clk~clkctrl altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg3 } { 0.000ns 0.000ns 0.139ns 1.151ns } { 0.000ns 1.100ns 0.000ns 0.835ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.267 ns + " "Info: + Micro hold delay of destination is 0.267 ns" {  } { { "db/altsyncram_77l.tdf" "" { Text "D:/work/add/db/altsyncram_77l.tdf" 43 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.490 ns - Shortest pin memory " "Info: - Shortest pin to memory delay is 9.490 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.904 ns) 0.904 ns Y\[3\] 1 PIN PIN_AB12 2 " "Info: 1: + IC(0.000 ns) + CELL(0.904 ns) = 0.904 ns; Loc. = PIN_AB12; Fanout = 2; PIN Node = 'Y\[3\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "" { Y[3] } "NODE_NAME" } "" } } { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.736 ns) + CELL(0.370 ns) 7.010 ns result~3 2 COMB LCCOMB_X25_Y1_N2 8 " "Info: 2: + IC(5.736 ns) + CELL(0.370 ns) = 7.010 ns; Loc. = LCCOMB_X25_Y1_N2; Fanout = 8; COMB Node = 'result~3'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "6.106 ns" { Y[3] result~3 } "NODE_NAME" } "" } } { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.101 ns) + CELL(0.370 ns) 8.481 ns Disp_Temp\[3\]~1352 3 COMB LCCOMB_X27_Y1_N10 1 " "Info: 3: + IC(1.101 ns) + CELL(0.370 ns) = 8.481 ns; Loc. = LCCOMB_X27_Y1_N10; Fanout = 1; COMB Node = 'Disp_Temp\[3\]~1352'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "1.471 ns" { result~3 Disp_Temp[3]~1352 } "NODE_NAME" } "" } } { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.833 ns) + CELL(0.176 ns) 9.490 ns altsyncram:Disp_Decode_rtl_0\|altsyncram_77l:auto_generated\|ram_block1a0~porta_address_reg3 4 MEM M4K_X26_Y1 7 " "Info: 4: + IC(0.833 ns) + CELL(0.176 ns) = 9.490 ns; Loc. = M4K_X26_Y1; Fanout = 7; MEM Node = 'altsyncram:Disp_Decode_rtl_0\|altsyncram_77l:auto_generated\|ram_block1a0~porta_address_reg3'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "1.009 ns" { Disp_Temp[3]~1352 altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg3 } "NODE_NAME" } "" } } { "db/altsyncram_77l.tdf" "" { Text "D:/work/add/db/altsyncram_77l.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.820 ns ( 19.18 % ) " "Info: Total cell delay = 1.820 ns ( 19.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.670 ns ( 80.82 % ) " "Info: Total interconnect delay = 7.670 ns ( 80.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "9.490 ns" { Y[3] result~3 Disp_Temp[3]~1352 altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg3 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "9.490 ns" { Y[3] Y[3]~combout result~3 Disp_Temp[3]~1352 altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg3 } { 0.000ns 0.000ns 5.736ns 1.101ns 0.833ns } { 0.000ns 0.904ns 0.370ns 0.370ns 0.176ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "3.225 ns" { Clk Clk~clkctrl altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg3 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "3.225 ns" { Clk Clk~combout Clk~clkctrl altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg3 } { 0.000ns 0.000ns 0.139ns 1.151ns } { 0.000ns 1.100ns 0.000ns 0.835ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "exp9" "UNKNOWN" "V1" "D:/work/add/db/exp9.quartus_db" { Floorplan "D:/work/add/" "" "9.490 ns" { Y[3] result~3 Disp_Temp[3]~1352 altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg3 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "9.490 ns" { Y[3] Y[3]~combout result~3 Disp_Temp[3]~1352 altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg3 } { 0.000ns 0.000ns 5.736ns 1.101ns 0.833ns } { 0.000ns 0.904ns 0.370ns 0.370ns 0.176ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}