packer.v

verilog data packer verilog data packer verilog data packer

/*******************************************************************/
/*   		This module implements Data packer Stage of the	       */
/*				Entropy Encoder					                   */
/*******************************************************************/

module packer( Reset,
               Enable,
               CodeandLength,
               Coefficient,
               Category,
               Clk,
               ValidCode,
               EOB,
               EndD, 
               DataOut,
               OutputValid,
               Ready
               );

/********************INPUTS***********************/
input [19:0] CodeandLength;    // Variable length Huffman Code and its Length
input [10:0] Coefficient;      // Variable length Coefficient
input [3:0]  Category;         // Category (Coefficient's length)
input        Clk;              // System wide clock
input        ValidCode;        // Arrival of Valid Data Signal.  The frequency of this
             // signal depends upon amount of compression being achieved in previous stages
input        Reset;            // System wide reset
input        EOB;              // Signal for End of Block
input        EndD;             // Signal for End of Data
input        Enable;           // System wide enable

/********************OUTPUTS**********************/
output[15:0] DataOut;          // Packed Output Data
output       OutputValid;      // Signals external logic that valid data is available
output       Ready;            // Signal showing if Data packer stage is ready or not

reg [15:0]   DataOut;
reg          OutputValid;	 
reg          Ready;		

/********************INTERNAL**********************/
reg [26:0]   RegA;            // These two registers hold data
reg [47:0]   RegB;            // for output
reg [4:0]    Length;          // Length Register contains lenght of valid data in RegA
reg [5:0]    EndP;            // It Points to end of valid data in RegB
						
reg          OutputLastData;  // Internal Signal
reg          ResetMe;         // Internal Reset
reg [15:0]   TempReg;         // Register for internal use
reg          EOB2, EOB3;	

wire [10:0] 	CoefficientIn, TempValue;
wire [3:0]		CodeLength;
wire 			ResetIt;
wire 			[15:0]Code;
wire 			[15:0] Data;
wire [5:0] 		Shift1, Shift2;

/*****************Extract Code and its length from CodeandLength***************/
assign Code = CodeandLength[15:0];         //Take Code from CodeandLength
assign CodeLength = CodeandLength[19:16];  //Take Code Length

/*****************Assignment of Output port************************/
assign Data = RegB[47:32];   //Output is taken from 16 upper bits of RegB 


/****************************************************************************************/
/*Value of Shift for Shifting contents of RegA to concatenate them with contents of RegB*/
/****************************************************************************************/
assign Shift1 = EndP - Length; 	

/****************************************************************************/
/* Value of Shift for Shifting contents of RegA in RegB when output is valid*/
/****************************************************************************/
assign Shift2 = (Shift1 + 16 );  // 16 more shifts are required b/c 16 bit of data has
                                 // been taken out of higher 16 bits of RegB

/**************Masking off of extra bits of Ceofficient*****************/
/********The Category contains length of valid bits in Coefficient******/
/*****Using Category garbage values in higher bits are masked off*******/
assign {CoefficientIn, TempValue}  = {Coefficient, 11'b 00000000000} & (22'b 0000000000011111111111 << Category);

/************Internally generated Reset***************/
assign ResetIt = Reset | ResetMe; //Reset = External Reset + Internal Reset



/********************************HANDLING OUTPUTS*******************************/
always @(posedge Clk or posedge ResetIt)
begin
if(ResetIt)
begin
	EndP <= 48;
	OutputValid <= 0;
end

else if(Enable)         // If pipeline is not freezed
begin
	if(ValidCode)       // If code has arrived in this clock cycle
	begin               // then take its length in Length register
		Length <= Category + CodeLength + 1;
	end                 // This register now contains length of data in RegA

	else
		Length <= 0;	

/****The variable length code and coefficients are concatenated and stored in RegA***/
/****All this is done even when no new code or category has come.  The same operation is 
***********************then performed at the old values*********/
	RegA <= CoefficientIn | (Code << Category);  // {Code, Coefficient}
					
	if(EndP < 33)                 // If there is valid data in upper
	begin                         // 16 bits of RegB
		OutputValid <= 1;         // Signal the output
		DataOut <= Data;          // Latch the higher 16 bits of RegB in DataOut

/**** Load new value in RegB with remaining bits shifted left 16 more times to fill ****/
/************************* the vaccancy created due to output***************************/
		RegB <= (RegB << 16) | ( RegA << Shift2 );
					
		EndP <= Shift2;          // Modify EndP to new end
	end

	else if(EOB3)                // If End of Block has arrived
	begin
		OutputValid <= 1;        // Signal the external circuitry
		OutputLastData <= 1;     // Set internal flag
                          // Padding of 1s in the remaining bits to create a 16 bit output
		{DataOut, TempReg} <= {RegB[47:32], 16'b 0000000000000000} | (32'b 00000000000000001111111111111111 << (EndP-16));	
	end

/*****************************************************************************************/
/*Arrive here when RegB contains less than 16 bits of data and EOB signal has not arrived*/
/*****************************************************************************************/
	else			 
	begin
	  	RegB <= RegB | ( RegA << Shift1);  
        //Concatenate new value in RegA with the previous ones in RegB

		EndP <= Shift1;              // and modify EndP to new end of valid data in RegB
		OutputValid <= 0;            //Output is invalid
	end

 end
 end

always @(posedge Clk or posedge ResetIt)
begin
if(ResetIt)	
begin	
	ResetMe <= 0;
	EOB2 <= 0;
	EOB3 <= 0;
end
else if(Enable) 
begin
	if(EOB)               // Temporary storage of EOB signal equal to no of stages
	begin                 // in data packer
		EOB2 <= 1;
	end
	else if(EOB3)         // so that till EOB reaches EOB3, data has reached RegB, the 
	begin                 // final destination from where it is to be output
		ResetMe <= 1;     // hence the remaining bits are then padded with 1s as specified
	end				      // in JPEG standard and output
	else if(EOB2)
	begin
		EOB3 <= 1;
	end
		
	if(OutputLastData )     // if last data has been output
	begin					
		if(EndD)            // of last block
			Ready <= 1;	    // tell this to external circuitry that the chip 
                            // has processed the data.  Pipeline is empty and
                            // ready for new set of data
		else                 
			Ready <= 0;     
	end
	
end
end

endmodule