my_nor.cxf

verilog 源代码 抑或门的程序很好用。。。。。。。。

<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>my_nor</name><vendor/><library/><version/><fileSets><fileSet fileSetId="OTHER_FILESET"><file fileid="0"><name>./my_nor.sdb</name><userFileType>SDB</userFileType></file></fileSet><fileSet fileSetId="HDL_FILESET"><file fileid="1"><name>./my_nor.v</name><fileType>verilogSource</fileType></file></fileSet><fileSet fileSetId="STIMULUS_FILESET"><file fileid="2"><name>./testbench.v</name><fileType>verilogSource</fileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>OTHER_FILESET</fileSetRef><fileSetRef>STIMULUS_FILESET</fileSetRef><name>OTHER</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel><category>SmartCoreDesign</category><function>SmartDesign</function><variation>SmartDesign</variation><vendor>Actel</vendor><version>1.0</version><vendorExtension><type>SmartCoreDesign</type></vendorExtension><vendorExtension><state value="GENERATED"/></vendorExtension><model><signals><signal><name>A</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>B</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>Y</name><direction>out</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal></signals></model></Component>