half_adder.ide_des

来自「verilog 加法器设计 在modelsim下方针。。。。。。。。。。。。。。」· IDE_DES 代码 · 共 20 行

KEY IDE_DES_TOOL "Designer"
KEY IDE_DES_FAMILY "ProASIC3"
KEY IDE_DES_DIE "IQ2X1M0"
KEY IDE_DES_PACKAGE "vq100"
KEY IDE_DES_TOP_CELL_NAME "half_adder"
KEY IDE_DES_KEEP_PHY_CONSTR "FALSE"
KEY IDE_DES_KEEP_TIME_CONSTR "TRUE"
KEY IDE_DES_LAYOUT_DONE "FALSE"
KEY IDE_DES_BA_EXPORTED "FALSE"
KEY IDE_DES_ERROR_FOUND "FALSE"
KEY IDE_DES_ADB_PATH "E:\work\EasyFPGA030\adder\designer\impl1\half_adder.adb"
LIST SOURCE_FILES
VALUE "E:\work\EasyFPGA030\adder\synthesis\half_adder.edn;edn"
VALUE "E:\work\EasyFPGA030\adder\synthesis\half_adder_sdc.sdc;sdc"
ENDLIST
LIST OPTIONAL_FILES
ENDLIST
LIST VCD_FILES
ENDLIST