maoci.tan.qmsg

用VHDL编的一个程序

{ "Info" "ITDB_TSU_RESULT" "clk_out~reg0 clk13 clk100 4.386 ns register " "Info: tsu for register \"clk_out~reg0\" (data pin = \"clk13\", clock pin = \"clk100\") is 4.386 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.251 ns + Longest pin register " "Info: + Longest pin to register delay is 7.251 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk13 1 PIN PIN_73 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_73; Fanout = 2; PIN Node = 'clk13'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk13 } "NODE_NAME" } } { "maoci.vhd" "" { Text "C:/Users/mayajun/Desktop/EDA/maoci/maoci.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.038 ns) + CELL(0.738 ns) 7.251 ns clk_out~reg0 2 REG LC_X5_Y1_N9 2 " "Info: 2: + IC(5.038 ns) + CELL(0.738 ns) = 7.251 ns; Loc. = LC_X5_Y1_N9; Fanout = 2; REG Node = 'clk_out~reg0'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.776 ns" { clk13 clk_out~reg0 } "NODE_NAME" } } { "maoci.vhd" "" { Text "C:/Users/mayajun/Desktop/EDA/maoci/maoci.vhd" 19 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.213 ns ( 30.52 % ) " "Info: Total cell delay = 2.213 ns ( 30.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.038 ns ( 69.48 % ) " "Info: Total interconnect delay = 5.038 ns ( 69.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.251 ns" { clk13 clk_out~reg0 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.251 ns" { clk13 clk13~out0 clk_out~reg0 } { 0.000ns 0.000ns 5.038ns } { 0.000ns 1.475ns 0.738ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "maoci.vhd" "" { Text "C:/Users/mayajun/Desktop/EDA/maoci/maoci.vhd" 19 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk100 destination 2.902 ns - Shortest register " "Info: - Shortest clock path from clock \"clk100\" to destination register is 2.902 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk100 1 CLK PIN_29 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 2; CLK Node = 'clk100'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk100 } "NODE_NAME" } } { "maoci.vhd" "" { Text "C:/Users/mayajun/Desktop/EDA/maoci/maoci.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.711 ns) 2.902 ns clk_out~reg0 2 REG LC_X5_Y1_N9 2 " "Info: 2: + IC(0.722 ns) + CELL(0.711 ns) = 2.902 ns; Loc. = LC_X5_Y1_N9; Fanout = 2; REG Node = 'clk_out~reg0'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.433 ns" { clk100 clk_out~reg0 } "NODE_NAME" } } { "maoci.vhd" "" { Text "C:/Users/mayajun/Desktop/EDA/maoci/maoci.vhd" 19 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 75.12 % ) " "Info: Total cell delay = 2.180 ns ( 75.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.722 ns ( 24.88 % ) " "Info: Total interconnect delay = 0.722 ns ( 24.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.902 ns" { clk100 clk_out~reg0 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.902 ns" { clk100 clk100~out0 clk_out~reg0 } { 0.000ns 0.000ns 0.722ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.251 ns" { clk13 clk_out~reg0 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.251 ns" { clk13 clk13~out0 clk_out~reg0 } { 0.000ns 0.000ns 5.038ns } { 0.000ns 1.475ns 0.738ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.902 ns" { clk100 clk_out~reg0 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.902 ns" { clk100 clk100~out0 clk_out~reg0 } { 0.000ns 0.000ns 0.722ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk100 clk_out clk_out~reg0 6.842 ns register " "Info: tco from clock \"clk100\" to destination pin \"clk_out\" through register \"clk_out~reg0\" is 6.842 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk100 source 2.902 ns + Longest register " "Info: + Longest clock path from clock \"clk100\" to source register is 2.902 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk100 1 CLK PIN_29 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 2; CLK Node = 'clk100'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk100 } "NODE_NAME" } } { "maoci.vhd" "" { Text "C:/Users/mayajun/Desktop/EDA/maoci/maoci.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.711 ns) 2.902 ns clk_out~reg0 2 REG LC_X5_Y1_N9 2 " "Info: 2: + IC(0.722 ns) + CELL(0.711 ns) = 2.902 ns; Loc. = LC_X5_Y1_N9; Fanout = 2; REG Node = 'clk_out~reg0'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.433 ns" { clk100 clk_out~reg0 } "NODE_NAME" } } { "maoci.vhd" "" { Text "C:/Users/mayajun/Desktop/EDA/maoci/maoci.vhd" 19 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 75.12 % ) " "Info: Total cell delay = 2.180 ns ( 75.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.722 ns ( 24.88 % ) " "Info: Total interconnect delay = 0.722 ns ( 24.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.902 ns" { clk100 clk_out~reg0 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.902 ns" { clk100 clk100~out0 clk_out~reg0 } { 0.000ns 0.000ns 0.722ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "maoci.vhd" "" { Text "C:/Users/mayajun/Desktop/EDA/maoci/maoci.vhd" 19 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.716 ns + Longest register pin " "Info: + Longest register to pin delay is 3.716 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_out~reg0 1 REG LC_X5_Y1_N9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y1_N9; Fanout = 2; REG Node = 'clk_out~reg0'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_out~reg0 } "NODE_NAME" } } { "maoci.vhd" "" { Text "C:/Users/mayajun/Desktop/EDA/maoci/maoci.vhd" 19 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.608 ns) + CELL(2.108 ns) 3.716 ns clk_out 2 PIN PIN_64 0 " "Info: 2: + IC(1.608 ns) + CELL(2.108 ns) = 3.716 ns; Loc. = PIN_64; Fanout = 0; PIN Node = 'clk_out'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.716 ns" { clk_out~reg0 clk_out } "NODE_NAME" } } { "maoci.vhd" "" { Text "C:/Users/mayajun/Desktop/EDA/maoci/maoci.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 56.73 % ) " "Info: Total cell delay = 2.108 ns ( 56.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.608 ns ( 43.27 % ) " "Info: Total interconnect delay = 1.608 ns ( 43.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.716 ns" { clk_out~reg0 clk_out } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.716 ns" { clk_out~reg0 clk_out } { 0.000ns 1.608ns } { 0.000ns 2.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.902 ns" { clk100 clk_out~reg0 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.902 ns" { clk100 clk100~out0 clk_out~reg0 } { 0.000ns 0.000ns 0.722ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.716 ns" { clk_out~reg0 clk_out } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.716 ns" { clk_out~reg0 clk_out } { 0.000ns 1.608ns } { 0.000ns 2.108ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "clk13_dly clk13 clk100 -3.898 ns register " "Info: th for register \"clk13_dly\" (data pin = \"clk13\", clock pin = \"clk100\") is -3.898 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk100 destination 2.902 ns + Longest register " "Info: + Longest clock path from clock \"clk100\" to destination register is 2.902 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk100 1 CLK PIN_29 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 2; CLK Node = 'clk100'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk100 } "NODE_NAME" } } { "maoci.vhd" "" { Text "C:/Users/mayajun/Desktop/EDA/maoci/maoci.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.711 ns) 2.902 ns clk13_dly 2 REG LC_X5_Y1_N5 1 " "Info: 2: + IC(0.722 ns) + CELL(0.711 ns) = 2.902 ns; Loc. = LC_X5_Y1_N5; Fanout = 1; REG Node = 'clk13_dly'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.433 ns" { clk100 clk13_dly } "NODE_NAME" } } { "maoci.vhd" "" { Text "C:/Users/mayajun/Desktop/EDA/maoci/maoci.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 75.12 % ) " "Info: Total cell delay = 2.180 ns ( 75.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.722 ns ( 24.88 % ) " "Info: Total interconnect delay = 0.722 ns ( 24.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.902 ns" { clk100 clk13_dly } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.902 ns" { clk100 clk100~out0 clk13_dly } { 0.000ns 0.000ns 0.722ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "maoci.vhd" "" { Text "C:/Users/mayajun/Desktop/EDA/maoci/maoci.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.815 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.815 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk13 1 PIN PIN_73 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_73; Fanout = 2; PIN Node = 'clk13'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk13 } "NODE_NAME" } } { "maoci.vhd" "" { Text "C:/Users/mayajun/Desktop/EDA/maoci/maoci.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.031 ns) + CELL(0.309 ns) 6.815 ns clk13_dly 2 REG LC_X5_Y1_N5 1 " "Info: 2: + IC(5.031 ns) + CELL(0.309 ns) = 6.815 ns; Loc. = LC_X5_Y1_N5; Fanout = 1; REG Node = 'clk13_dly'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.340 ns" { clk13 clk13_dly } "NODE_NAME" } } { "maoci.vhd" "" { Text "C:/Users/mayajun/Desktop/EDA/maoci/maoci.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.784 ns ( 26.18 % ) " "Info: Total cell delay = 1.784 ns ( 26.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.031 ns ( 73.82 % ) " "Info: Total interconnect delay = 5.031 ns ( 73.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.815 ns" { clk13 clk13_dly } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.815 ns" { clk13 clk13~out0 clk13_dly } { 0.000ns 0.000ns 5.031ns } { 0.000ns 1.475ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.902 ns" { clk100 clk13_dly } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.902 ns" { clk100 clk100~out0 clk13_dly } { 0.000ns 0.000ns 0.722ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.815 ns" { clk13 clk13_dly } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.815 ns" { clk13 clk13~out0 clk13_dly } { 0.000ns 0.000ns 5.031ns } { 0.000ns 1.475ns 0.309ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "136 " "Info: Allocated 136 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 08 11:10:54 2009 " "Info: Processing ended: Wed Apr 08 11:10:54 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}