maoci.tan.rpt

用VHDL编的一个程序

; Slack ; Required tsu ; Actual tsu ; From  ; To           ; To Clock ;
+-------+--------------+------------+-------+--------------+----------+
; N/A   ; None         ; 4.386 ns   ; clk13 ; clk_out~reg0 ; clk100   ;
; N/A   ; None         ; 3.950 ns   ; clk13 ; clk13_dly    ; clk100   ;
+-------+--------------+------------+-------+--------------+----------+


+-------------------------------------------------------------------------+
; tco                                                                     ;
+-------+--------------+------------+--------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To      ; From Clock ;
+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 6.842 ns   ; clk_out~reg0 ; clk_out ; clk100     ;
+-------+--------------+------------+--------------+---------+------------+


+---------------------------------------------------------------------------+
; th                                                                        ;
+---------------+-------------+-----------+-------+--------------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To           ; To Clock ;
+---------------+-------------+-----------+-------+--------------+----------+
; N/A           ; None        ; -3.898 ns ; clk13 ; clk13_dly    ; clk100   ;
; N/A           ; None        ; -4.334 ns ; clk13 ; clk_out~reg0 ; clk100   ;
+---------------+-------------+-----------+-------+--------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Wed Apr 08 11:10:53 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off maoci -c maoci --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk100" is an undefined clock
Info: Clock "clk100" Internal fmax is restricted to 275.03 MHz between source register "clk_out~reg0" and destination register "clk_out~reg0"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.014 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y1_N9; Fanout = 2; REG Node = 'clk_out~reg0'
            Info: 2: + IC(0.536 ns) + CELL(0.478 ns) = 1.014 ns; Loc. = LC_X5_Y1_N9; Fanout = 2; REG Node = 'clk_out~reg0'
            Info: Total cell delay = 0.478 ns ( 47.14 % )
            Info: Total interconnect delay = 0.536 ns ( 52.86 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk100" to destination register is 2.902 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 2; CLK Node = 'clk100'
                Info: 2: + IC(0.722 ns) + CELL(0.711 ns) = 2.902 ns; Loc. = LC_X5_Y1_N9; Fanout = 2; REG Node = 'clk_out~reg0'
                Info: Total cell delay = 2.180 ns ( 75.12 % )
                Info: Total interconnect delay = 0.722 ns ( 24.88 % )
            Info: - Longest clock path from clock "clk100" to source register is 2.902 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 2; CLK Node = 'clk100'
                Info: 2: + IC(0.722 ns) + CELL(0.711 ns) = 2.902 ns; Loc. = LC_X5_Y1_N9; Fanout = 2; REG Node = 'clk_out~reg0'
                Info: Total cell delay = 2.180 ns ( 75.12 % )
                Info: Total interconnect delay = 0.722 ns ( 24.88 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "clk_out~reg0" (data pin = "clk13", clock pin = "clk100") is 4.386 ns
    Info: + Longest pin to register delay is 7.251 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_73; Fanout = 2; PIN Node = 'clk13'
        Info: 2: + IC(5.038 ns) + CELL(0.738 ns) = 7.251 ns; Loc. = LC_X5_Y1_N9; Fanout = 2; REG Node = 'clk_out~reg0'
        Info: Total cell delay = 2.213 ns ( 30.52 % )
        Info: Total interconnect delay = 5.038 ns ( 69.48 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk100" to destination register is 2.902 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 2; CLK Node = 'clk100'
        Info: 2: + IC(0.722 ns) + CELL(0.711 ns) = 2.902 ns; Loc. = LC_X5_Y1_N9; Fanout = 2; REG Node = 'clk_out~reg0'
        Info: Total cell delay = 2.180 ns ( 75.12 % )
        Info: Total interconnect delay = 0.722 ns ( 24.88 % )
Info: tco from clock "clk100" to destination pin "clk_out" through register "clk_out~reg0" is 6.842 ns
    Info: + Longest clock path from clock "clk100" to source register is 2.902 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 2; CLK Node = 'clk100'
        Info: 2: + IC(0.722 ns) + CELL(0.711 ns) = 2.902 ns; Loc. = LC_X5_Y1_N9; Fanout = 2; REG Node = 'clk_out~reg0'
        Info: Total cell delay = 2.180 ns ( 75.12 % )
        Info: Total interconnect delay = 0.722 ns ( 24.88 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 3.716 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y1_N9; Fanout = 2; REG Node = 'clk_out~reg0'
        Info: 2: + IC(1.608 ns) + CELL(2.108 ns) = 3.716 ns; Loc. = PIN_64; Fanout = 0; PIN Node = 'clk_out'
        Info: Total cell delay = 2.108 ns ( 56.73 % )
        Info: Total interconnect delay = 1.608 ns ( 43.27 % )
Info: th for register "clk13_dly" (data pin = "clk13", clock pin = "clk100") is -3.898 ns
    Info: + Longest clock path from clock "clk100" to destination register is 2.902 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 2; CLK Node = 'clk100'
        Info: 2: + IC(0.722 ns) + CELL(0.711 ns) = 2.902 ns; Loc. = LC_X5_Y1_N5; Fanout = 1; REG Node = 'clk13_dly'
        Info: Total cell delay = 2.180 ns ( 75.12 % )
        Info: Total interconnect delay = 0.722 ns ( 24.88 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 6.815 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_73; Fanout = 2; PIN Node = 'clk13'
        Info: 2: + IC(5.031 ns) + CELL(0.309 ns) = 6.815 ns; Loc. = LC_X5_Y1_N5; Fanout = 1; REG Node = 'clk13_dly'
        Info: Total cell delay = 1.784 ns ( 26.18 % )
        Info: Total interconnect delay = 5.031 ns ( 73.82 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 136 megabytes of memory during processing
    Info: Processing ended: Wed Apr 08 11:10:54 2009
    Info: Elapsed time: 00:00:01