maoci.vhd

来自「用VHDL编的一个程序」· VHDL 代码 · 共 29 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity maoci is
       Port (clk13,clk100:in std_logic;
             clk_out:out std_logic      
             );
end maoci;

    
architecture Behavioral of maoci is   
signal clk13_dly:std_logic;
begin

process(clk100)
begin 
if(clk100'event and clk100='1') then
	clk13_dly<=clk13;
	if(clk13='1' and clk13_dly='1') then
	  clk_out<='1';
	elsif(clk13='0' and clk13_dly='0') then
	  clk_out<='0';
	end if;
end if;
end process;

end Behavioral;