recv.fit.qmsg

来自「很多仪器都输出同步时钟」· QMSG 代码 · 共 39 行 · 第 1/5 页

{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clk Global clock in PIN 29 " "Info: Automatically promoted some destinations of signal \"clk\" to use Global clock in PIN 29" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "wrclk " "Info: Destination \"wrclk\" may be non-global or may not use global clock" {  } { { "recv_top.vhd" "" { Text "E:/课题/预警/recv/recv_top.vhd" 16 -1 0 } }  } 0}  } { { "recv_top.vhd" "" { Text "E:/课题/预警/recv/recv_top.vhd" 14 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "recv_core:U_Core1\|reset_parts Global clock " "Info: Automatically promoted signal \"recv_core:U_Core1\|reset_parts\" to use Global clock" {  } { { "recv_core.vhd" "" { Text "E:/课题/预警/recv/recv_core.vhd" 20 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "recv_core:U_Core1\|reset_dt Global clock " "Info: Automatically promoted signal \"recv_core:U_Core1\|reset_dt\" to use Global clock" {  } { { "recv_core.vhd" "" { Text "E:/课题/预警/recv/recv_core.vhd" 18 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}