recv.tan.qmsg

很多仪器都输出同步时钟

{ "Info" "ITDB_TH_RESULT" "shift_register1:U_SR1\|shift_regs\[68\] RxD clk -4.730 ns register " "Info: th for register \"shift_register1:U_SR1\|shift_regs\[68\]\" (data pin = \"RxD\", clock pin = \"clk\") is -4.730 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.925 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 215 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 215; CLK Node = 'clk'" {  } { { "E:/课题/预警/recv/db/recv_cmp.qrpt" "" { Report "E:/课题/预警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/课题/预警/recv/db/recv.quartus_db" { Floorplan "E:/课题/预警/recv/" "" "" { clk } "NODE_NAME" } "" } } { "recv_top.vhd" "" { Text "E:/课题/预警/recv/recv_top.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns shift_register1:U_SR1\|shift_regs\[68\] 2 REG LC_X16_Y12_N7 1 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X16_Y12_N7; Fanout = 1; REG Node = 'shift_register1:U_SR1\|shift_regs\[68\]'" {  } { { "E:/课题/预警/recv/db/recv_cmp.qrpt" "" { Report "E:/课题/预警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/课题/预警/recv/db/recv.quartus_db" { Floorplan "E:/课题/预警/recv/" "" "1.456 ns" { clk shift_register1:U_SR1|shift_regs[68] } "NODE_NAME" } "" } } { "shift_register1.vhd" "" { Text "E:/课题/预警/recv/shift_register1.vhd" 25 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.53 % " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns 25.47 % " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0}  } { { "E:/课题/预警/recv/db/recv_cmp.qrpt" "" { Report "E:/课题/预警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/课题/预警/recv/db/recv.quartus_db" { Floorplan "E:/课题/预警/recv/" "" "2.925 ns" { clk shift_register1:U_SR1|shift_regs[68] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 shift_register1:U_SR1|shift_regs[68] } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "shift_register1.vhd" "" { Text "E:/课题/预警/recv/shift_register1.vhd" 25 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.670 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.670 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns RxD 1 PIN PIN_214 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_214; Fanout = 2; PIN Node = 'RxD'" {  } { { "E:/课题/预警/recv/db/recv_cmp.qrpt" "" { Report "E:/课题/预警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/课题/预警/recv/db/recv.quartus_db" { Floorplan "E:/课题/预警/recv/" "" "" { RxD } "NODE_NAME" } "" } } { "recv_top.vhd" "" { Text "E:/课题/预警/recv/recv_top.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.886 ns) + CELL(0.309 ns) 7.670 ns shift_register1:U_SR1\|shift_regs\[68\] 2 REG LC_X16_Y12_N7 1 " "Info: 2: + IC(5.886 ns) + CELL(0.309 ns) = 7.670 ns; Loc. = LC_X16_Y12_N7; Fanout = 1; REG Node = 'shift_register1:U_SR1\|shift_regs\[68\]'" {  } { { "E:/课题/预警/recv/db/recv_cmp.qrpt" "" { Report "E:/课题/预警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/课题/预警/recv/db/recv.quartus_db" { Floorplan "E:/课题/预警/recv/" "" "6.195 ns" { RxD shift_register1:U_SR1|shift_regs[68] } "NODE_NAME" } "" } } { "shift_register1.vhd" "" { Text "E:/课题/预警/recv/shift_register1.vhd" 25 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.784 ns 23.26 % " "Info: Total cell delay = 1.784 ns ( 23.26 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.886 ns 76.74 % " "Info: Total interconnect delay = 5.886 ns ( 76.74 % )" {  } {  } 0}  } { { "E:/课题/预警/recv/db/recv_cmp.qrpt" "" { Report "E:/课题/预警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/课题/预警/recv/db/recv.quartus_db" { Floorplan "E:/课题/预警/recv/" "" "7.670 ns" { RxD shift_register1:U_SR1|shift_regs[68] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.670 ns" { RxD RxD~out0 shift_register1:U_SR1|shift_regs[68] } { 0.000ns 0.000ns 5.886ns } { 0.000ns 1.475ns 0.309ns } } }  } 0}  } { { "E:/课题/预警/recv/db/recv_cmp.qrpt" "" { Report "E:/课题/预警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/课题/预警/recv/db/recv.quartus_db" { Floorplan "E:/课题/预警/recv/" "" "2.925 ns" { clk shift_register1:U_SR1|shift_regs[68] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 shift_register1:U_SR1|shift_regs[68] } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/课题/预警/recv/db/recv_cmp.qrpt" "" { Report "E:/课题/预警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/课题/预警/recv/db/recv.quartus_db" { Floorplan "E:/课题/预警/recv/" "" "7.670 ns" { RxD shift_register1:U_SR1|shift_regs[68] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.670 ns" { RxD RxD~out0 shift_register1:U_SR1|shift_regs[68] } { 0.000ns 0.000ns 5.886ns } { 0.000ns 1.475ns 0.309ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu May 18 20:05:44 2006 " "Info: Processing ended: Thu May 18 20:05:44 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}