recv_package.vhd

来自「很多仪器都输出同步时钟」· VHDL 代码 · 共 54 行

-- 库声明
library IEEE;
use IEEE.STD_LOGIC_1164.all; 

-- 包声明
PACKAGE RECV_PACKAGE IS	 
	
-- 信号监测器状态
type dt_state is 
(
dt_unlock,			-- 未锁定状态
dt_lock 			-- 锁定状态
);	 

-- UART状态
type UART_STATE is
( 
UART_IDLE,
UART_RECV,
UART_END_RECV,
SEND_BACK
);

type PARITY is
(
NONE,
ODD,
EVEN
);
-- 函数声明
function MultiXOR(
	din : in std_logic_vector )
  	return std_logic;

END RECV_PACKAGE;

-- 包体
PACKAGE BODY RECV_PACKAGE IS

-- 函数实现
function MultiXOR(
	din : in std_logic_vector )
  	return std_logic is
	variable check : std_logic;
begin
	check := din(din'LOW);
	for i in 1 to (din'HIGH) loop
		check := check xor din(i);
	end loop;
		
	return check;
end MultiXOR;

END RECV_PACKAGE;