spitest.map.rpt

很多仪器都输出同步时钟

Analysis & Synthesis report for SPITEST
Thu Apr 27 15:34:52 2006
Version 5.0 Build 148 04/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. General Register Statistics
  9. Inverted Register Statistics
 10. Multiplexer Restructuring Statistics (Restructuring Performed)
 11. Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0
 12. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 13. SignalTap II Logic Analyzer Settings
 14. Analysis & Synthesis Equations
 15. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Apr 27 15:34:52 2006    ;
; Quartus II Version          ; 5.0 Build 148 04/26/2005 SJ Full Version ;
; Revision Name               ; SPITEST                                  ;
; Top-level Entity Name       ; spitest                                  ;
; Family                      ; Cyclone                                  ;
; Total logic elements        ; 1,168                                    ;
; Total pins                  ; 127                                      ;
; Total virtual pins          ; 0                                        ;
; Total memory bits           ; 18,688                                   ;
; Total PLLs                  ; 0                                        ;