dm642_syn.tan.summary

一个用vHDL语言编的同步程序

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 7.696 ns
From           : syn_dm642~reg0
To             : syn_dm642
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 209.95 MHz ( period = 4.763 ns )
From           : syn_count[7]
To             : syn_count[17]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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